摘要
流水线ADC使用数字校正算法来提高精度。与传统的数字校正算法不同,基于统计的数字校正算法是在产生双余量曲线的基础上完成的,所以,双余量曲线的产生至关重要。Verilog-A为模拟电路提供了一种自顶向下的设计方法,在短时间内验证设计者的思想,提高工作效率。利用Verilog-A,对双余量曲线产生模块建模,采用Cadence的Spectre仿真器,对建立的行为模型进行仿真验证。
Digital correction algorithm is usually used to improve resolution of pipelined A/D converter.Different from the conventional correction method,the statistics based digital correction method is realized by generating two-residue curves,which is very important.Modeling of two-residue generation circuit was done using Verilog-A,which could provide a top-down design method for analog circuit and system.And the established behavioral model was verified with Spectre of Cadence.
出处
《微电子学》
CAS
CSCD
北大核心
2010年第6期880-883,889,共5页
Microelectronics
