期刊文献+

十亿晶体管级芯片系统集成面临的挑战与机遇 被引量:2

Challenges and opportunities in billion-transistor system-on-a-chip integration
下载PDF
导出
摘要 概述了半导体工业的发展趋势 ,讨论了 1 0亿晶体管级芯片系统所面临的挑战 ,并提出了若干研究课题以获得即将来临的纳米时代的发展机遇。 The roadmap of semiconductor industry is reviewed in this paper.The challenges on the billion transistor integration of system on a chip are addressed and finally research projects are suggested to help us holding the opportunities in the coming nanometer era.
出处 《半导体情报》 2001年第1期2-4,共3页 Semiconductor Information
基金 国家重大基础研究发展规划!( G19990 3 2 90 2 ) 国家自然科学基金!( 69973 0 2 7)
关键词 芯片系统 可重构系统 集成电路 晶体管 system on a chip reconfigurable systems design and verification of IC design reuse
  • 相关文献

参考文献8

  • 1Semiconductor Industry Association (SIA). International Technology Roadmap for Semiconductors, 1999; 被引量:1
  • 2De Man H. System-on-Chip Design: Impact on Education and Research. IEEE Design & Test of Computers, 1999; (7~9): 11 被引量:1
  • 3Semiconductor Research Corporation. Research Need for Circuit Design. SRC Design Sciences, 1999; 被引量:1
  • 4Cong J. Challenges and Opportunities for Design Innovations in Nanometer Technologies. SRC Design Sciences Concept Paper,1997; (12) 被引量:1
  • 5Cong J. NSF/NSC Joint Workshop on Challenges and Opportunities in Giga-Scale Integration for System on-A-Chip. 1999; (8):24 被引量:1
  • 6Maly W. IC Design and Test Research Directions Derived from the 1997 SIA Roadmap Version. 1999; 被引量:1
  • 7What Is The Proper System on Chip Design Methodology?, a Panel Discussion. ACM/IEEE Design Automation Conference,New Orleans, 1999; (6): 21 被引量:1
  • 8RF Integrateion into CMOS and Deep-Submicron Challenges, a D&T Rountable. IEEE Design Test of Computers, 1999; (7~9): 112 被引量:1

同被引文献6

  • 1Chang H, Kundert K. Verification of complex analog and RF IC designs [J]. Proceedings of the IEEE, 2007,95 (3) ~ 622-639. 被引量:1
  • 2Liang C,Zhong G, Huang S, et al. UVM-AMS based sub-system verification of wireless power receiver SoC [C]// Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on. China, Guilin,IEEE, 2014: 1-3. 被引量:1
  • 3Janick Bergeron. Writing testbench using system veril- og[M~. Berlin: Synopsys, Inc, Springer, 2008. 被引量:1
  • 4Srikanth Vijayaraghavan, Meyyappan RamanatharLSystemVerilogAssertions应用指南[M].陈俊杰,译.北京:清华大学出版社,2006. 被引量:1
  • 5Accellera. Verilog-AMS language reference manual I-M]. Napa, Accellera Systems Initiative Inc. 2014. 被引量:1
  • 6田劲,王小力.基于UVM验证方法学的AES模块级验证[J].微电子学与计算机,2012,29(8):86-90. 被引量:15

引证文献2

二级引证文献3

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部