摘要
提出了一种由调制信号产生电路、比较锁存电路、输出级电路组成的嵌入式动态锁存比较器。该比较器结构简单、面积小,采用一套可控时钟,在减小功耗的基础上得到了高精度。电路在MXIC 0.5μm标准CMOS工艺上流片实现。芯片测试结果表明,该比较器在±5V电源电压,128kHz工作频率下,输入失调电压9mV,可比较2.63mV以下电压差,功耗仅为49μW。比较器芯片尺寸为130μm×225μm,速度最高可达到5MHz,完全满足工程应用需求。
An embedded CMOS dynamic latch comparator consisting of modulation signal generator circuit, comparative latch circuit and output stage was presented. Fabricated in MXIC 0. 5 μm CMOS standard technology, the comparator had a simple structure and small layout area. In this circuit, a set of controlled clock was used to reduce power and improve resolution. Test results showed that the comparator achieved an input offset voltage of 9 mV at ± 5 V supply voltage and 128 kHz clock frequency with only 49 μW of power, and it could effectively distinguish voltage of 0. 5 mV. The comparator occupied a chip area of 130 μm X 225 μm, and its operating frequency reached up to 5 MHz.
出处
《微电子学》
CAS
CSCD
北大核心
2013年第6期802-806,共5页
Microelectronics
基金
中国科学技术部国家重大科技项目(20112x05008-005-04-02)
国家自然科学基金资助项目(61233010)
湖南省自然科学基金资助项目(12JJ4064)
