摘要
为了适应新的数字信号处理技术的发展,采用FPGA实现技术设计了串行RapidIO高速串行传输接口,实现了DSP与FPGA之间、FPGA与FPGA之间的高速数据传输,详细介绍了本地端点设备访问和远端设备访问的时序设计过程。对RapidIO总线的性能指标进行了测试,试验表明,在1lane、全双工模式下,数据传输速率可达243MB/S,突破了以前DSP的外部接口总线的传输速度瓶颈。
The high-speed serial RapidIO interface is designed based on FPGA in order to adapt the development of digital signal process technology. Based on this design, the high-speed data transmission between DSP and FPGA, FPGA and FPGA is realized. This paper introduces in detail the design of local access timing and remote access timing. The performance of RapidIO bus is tested, and the results show that the data transmission rate can be up to 243MB/s in 1 lane and full-duplex mode, breaking through the bottleneck of the DSP IO transfer speed.
出处
《计算机与网络》
2012年第13期57-59,共3页
Computer & Network
