摘要
针对一种基于PCI Express和Serial RapidIO混合式互连架构的硬件加速系统,介绍了其中基于FPGA实现的低延迟、多通道、跨平台的PCIe-SRIO桥接方法。介绍了该PCIe-SRIO桥的逻辑架构,详细叙述了数据调度方法,给出了系统实现成果以及性能测试结果。该成果解决了标准计算机与硬件加速部件的高速接口问题,比同功能的专用ASIC器件具有更好的适应性以及扩展性。
This paper presents a hybrid interconnection architecture based on both PCI Express and Serial RapidIO for hardware acceleration applications. It introduces a low-latency, multi-channels and platform-compatibility PCIe-SRIO bridge running in FPGA. This paper introduces the logic architecture of the PCIe-SRIO bridge, describes the data scheduling method in details, and provides the system implementation and performance test results. This PCIe-SRIO bridge can provide high speed interface between standard computers and hardware accelerators, and it has better adaptability and expansibility than ASIC devices with the same function.
出处
《电子设计工程》
2017年第15期189-193,共5页
Electronic Design Engineering
