摘要
针对实时高速信号处理要求,设计并实现了一种基于FPGA的高速流水线结构的基4FFT处理器。根据各种不同基算法的运算量、硬件面积和控制复杂度,选定按时间抽取的基4算法,同时采用单路延时反馈(Single-path Delay Feedback,SDF)流水线结构,提高了处理速度。通过Verilog HDL语言进行模块化描述和验证,结果表明,该FFT处理器具有较高性能。
A high-speed FFT processor based on FPGA is designed and realized to meet the demand of real time and high speed signal processing. Based on the analysis of the FFT algorithm, hardware area and complexity of control, the proposed processor adopts radix-4 DIT algorithm and a Single-path Delay Feedback （SDF） pipelined architecture, which speeds up the signal processing. The entire design is described, verified and implemented in Verilog HDL language. The results show that this FFT processor has higher performance.
出处
《物联网技术》
2012年第7期38-40,44,共4页
Internet of things technologies
关键词
FFT
流水线
基4
蝶形运算
FFT
pipeline
radix-4
butterfly computing
