摘要
介绍了利用NIOSⅡ软核处理器设计嵌入式测试系统的两类系统架构,详细讲述了基于NIOSⅡ软核处理器的嵌入式测试系统软硬件设计方法;最后结合EP2C8Q-208C8型FPGA芯片,利用Verilog语言描述A/D芯片的工作时序逻辑,利用NIOSⅡ软核处理器设计串口处理单元,将A/D采集的数据通过串口发送到计算机显示。实践表明,利用NIOS II软核处理器设计嵌入式测试系统,具有开发周期短,系统集成度高,功能灵活多样等特点,与传统利用单片机设计嵌入式测试系统相比,具有时钟频率高、运行速度快、调试方便等特点,是一种值得推广的嵌入式测试系统设计方法。
The two types embedded test system architectures that designed in the use of NIOS II soft-core processor are introduced in this topic,embedded test system hardware and software design based on NIOS II soft-core processor is described in detail.Finally,with EP2C8Q-208C8 FPGA,we use Verilog language to describe operating timing logic of A / D chip,use NIOS II soft core processor to design serial processing unit,and transferring data which the A / D chip samples through the serial port to the computer and display data.Practice shows that the method that using NIOS II soft-core processor to design embedded test system,it has features of short development cycle,highly integrated system,flexible feature and so on,contrasting the traditional embedded test system design based on single chip-computer,it has features of high clock frequency,high speed running,convenient debugging,it is a worthy design of embedded test system.
出处
《计算机测量与控制》
CSCD
北大核心
2012年第2期303-306,共4页
Computer Measurement &Control
