摘要
随着媒体处理和科学计算等应用领域数据级并行性的需求不断增加,SIMD体系结构以其固有的易扩展数据并行处理结构被广泛采用且系统规模日益增大,这使得SIMD体系结构的仿真测试逐渐成为难题,仿真速度与成本的矛盾加剧。本文提出了一种适用于SIMD体系结构的多时钟耦合仿真技术,它采用多个不同频率的时钟分别控制仿真系统的不同功能模块,实现计算单元的分时复用。实验结果表明,多时钟耦合仿真技术能有效提高FPGA芯片的仿真能力,增强仿真系统的灵活可配置性,降低了硬件仿真的成本。
As the DLP requirement of the applications such as multimedia and complicated scientific computing increasing quickly, SIMD architecture has been widely adopted due to its intrinsic well scalable data-parallel structure. The contradiction between the cost and speed of the SIMD architecture simulation is remarked as the SIMD system scales. In this paper, Multi-Clock Coupling Simulation Technology is proposed, which uses multi-clocks in different frequencies to control different part of the SIMD simulation system respectively to make the computing units work in time-multiplexing mode. The results of the experiment show that Multi-Clock Coupling Simulation Technology can effectively reduce the FPGA resource consuming of the SIMD simultation system and make the simultation system more flexible and well configtrable.
出处
《软件》
2011年第9期45-48,共4页
Software
基金
国家863专题课题(2009AA01Z102)
国家自然科学基金(61040021)
