摘要
通过对二值单稳态触发器设计原理的重新归纳，本文从三值三稳态触发器的正确设计出发，提出了二种三值单稳态触发器的设计方案。以RC微分电路为定时电路的设计已用PSPICE程序进行计算机验证。结果表明所设计的二种三值单稳态触发器具有正确的功能。与二值单稳态触发器相比，它们具有更强的功能并能在实用设计中获得更广泛的应用。
Starting from the fundamental design principle of binary mon0-stable flip-flops, this paper proposes twodesigns of ternary mono-stable flip-flops, which are based on the design of ternary three-stable-state flip-flops. These twodesigns using RC differential circuit as the timer unit are verified by PSPICE simulation. Simulation result proves that twokinds of ternary mon0-stable flip-flops have correct logic function. Compared with binary mono-stable flip-flops, ternarymono-stable flip-flops have robust function and can be widely applied into design practice.
出处
《电路与系统学报》
CSCD
1999年第4期91-94,共4页
Journal of Circuits and Systems
基金
浙江省自然科学基金
宁波市青年科学基金
关键词
单稳态触发器
电路设计
数字电路
Multi-valued logic, Ternary mono-stable flip-flops, Circuit design
