期刊文献+

Physical Implementation of the Eight-Core Godson-3B Microprocessor

Physical Implementation of the Eight-Core Godson-3B Microprocessor
原文传递
导出
摘要 The Godson-3B processor is a powerful processor designed for high performance servers including Dawning Servers. It offers significantly improved performance over previous Godson-3 series CPUs by incorporating eight CPU cores and vector computing units. It contains 582.6 M transistors within 300 mm2 area in 65 nm technology and is implemented in parallel with full hierarchical design flows. In Godson-3B, advanced clock distribution mechanisms including GALS (Globally Asynchronous Locally Synchronous) and clock mesh are adopted to obtain an OCV tolerable clock network. Custom-designed de-skew modules are also implemented to afford further latency balance after fabrication. The power reduction of Godson- 3B is maintained by MLMM (Multi Level Multi Mode) clock gating and multi-threshold-voltage cells substitution schemes. The highest frequency of Godson-3B is 1.05 GHz and the peak performance is 128 GFlops (double-precision) or 256 GFlops (single-precision) with 40 W power consumption. The Godson-3B processor is a powerful processor designed for high performance servers including Dawning Servers. It offers significantly improved performance over previous Godson-3 series CPUs by incorporating eight CPU cores and vector computing units. It contains 582.6 M transistors within 300 mm2 area in 65 nm technology and is implemented in parallel with full hierarchical design flows. In Godson-3B, advanced clock distribution mechanisms including GALS (Globally Asynchronous Locally Synchronous) and clock mesh are adopted to obtain an OCV tolerable clock network. Custom-designed de-skew modules are also implemented to afford further latency balance after fabrication. The power reduction of Godson- 3B is maintained by MLMM (Multi Level Multi Mode) clock gating and multi-threshold-voltage cells substitution schemes. The highest frequency of Godson-3B is 1.05 GHz and the peak performance is 128 GFlops (double-precision) or 256 GFlops (single-precision) with 40 W power consumption.
出处 《Journal of Computer Science & Technology》 SCIE EI CSCD 2011年第3期520-527,共8页 计算机科学技术学报(英文版)
基金 supported by the Important National Science and Technology Specific Projects under Grant Nos. 2009ZX01028-002-003,2009ZX01029-001-003,2010ZX01036-001-002 the National Natural Science Foundation of China under Grant Nos. 61050002,60736012,60921002,61003064
关键词 physical implementation hierarchical design flow GALS clock mesh low power physical implementation, hierarchical design flow, GALS, clock mesh, low power
  • 相关文献

参考文献2

二级参考文献12

  • 1Wei-WuHu Fu-XinZhang Zu-SongLi.Microarchitecture of the Godson-2 Processor[J].Journal of Computer Science & Technology,2005,20(2):243-249. 被引量:52
  • 2Wilke G R,Murgai R.Design and analysis of"tree+local meshes"clock architecture[].Proceedings of the International Symposium on Quality Electronic Design.2007 被引量:1
  • 3Chen H,Yeh C,Wilke G,et al.Asliding windowscheme for accurate clock Mesh analysis[].Proceedings of the IEEE/ACMInternational Conference on Computer-Aided Design.2005 被引量:1
  • 4Reddy S M,Wilke G R,Rajeev M.Analyzing timing uncertainty in Mesh-based clock architectures[].Proceedings of DesignAutomation and Test in Europe Conference and Exhibition.2006 被引量:1
  • 5Mori M,Chen H Y,Yao B,et al.A multiple level network approach for clock skew minimization with process variations[].Proceedings of the Asia and South Pacific Design Automation Conference.2004 被引量:1
  • 6Zou Y,Zhou Q,Cai Y,et al.Analysis of buffered hybrid structured clock networks[].Proceedings of the Asia and South Pacific Design Automation Conference.2005 被引量:1
  • 7Blaauw D,,Srivastava A.Statistical timing analysis:from basic principles to state of the art[].IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems.2008 被引量:1
  • 8P. S. Zuchowski,P. A. Habitz,J. D. Hayes,,J. H. Oppold."Process and environmental variability impacts on ASIC timing,"[].Proc of International Conference on Computer- Aided Design.2004 被引量:1
  • 9Stolt B,Mittlefehldtm Y,Dubey S,Mittal G,Lee M,Friedrich J,Fluhr E.Design and implementation of the Power6 microprocessor[].IEEE Journal of Solid State Circuits.2008 被引量:1
  • 10Hu WW,Wang J,Gao X,et al.GODSON-3:A scalable multicore RISC processor with X86 emulation[].IEEE Micro Magazine.2009 被引量:1

共引文献15

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部