摘要
介绍了基于数字电视基带SoC芯片的可测性设计方案。根据系统中不同模块的特点采取有针对性的可测性设计方案,对片内存储器进行内建自测试;对组合逻辑电路、时序逻辑电路采用近全扫描的测试方案;最后采用IEEE1149.1的控制单元作为芯片可测性设计部分的控制单元,控制芯片的测试功能。经测试,该可测性设计满足设计规划的面积和功耗的要求,并且系统的测试覆盖率达到了99.26%。
The features of the testability design of DTV baseband SoC chip are described. It has specific testability features for different modules in the system. Memory Build-in-Self-Test （BIST） is implemented for testing and diagnosing embedded SRAM, and almost full scan test scheme is carried out for combinational and sequential logic circuits. Additionally, the architecture facilitates IEEE1149.1 as a controller to access all test features. The testing results show that the DFT design can satisfy the requirement on area and power. Besides, the test coverage of system is up to 99.26%.
出处
《电视技术》
北大核心
2010年第7期47-49,73,共4页
Video Engineering
