摘要
介绍了一种运用于带通Σ-Δ调制器的谐振频率为25MHz的低功耗开关电容DD谐振器电路.电路采用了运算放大器共享技术和双采样技术,同时对单元电路进行优化,达到功耗最小化.该谐振器电路采用SMIC0.25μm混合信号CMOS工艺进行设计,整个电路模块面积仅为0.09mm2.测试结果表明,使用该谐振器电路的带通Σ-Δ调制器工作于100MHz采样频率时,对于信号带宽为1kHz的输入信号,调制器的输出在谐振频率处SFDR约为77dB.整个谐振器功耗为10.5mW.
A low power switched-capacitor double-delay （DD） topology resonator with the resonance frequency of 25 MHz is presented. By using OPAMP sharing technique,double-sampling technique and low power unit circuit blocks,the power consumption of the resonator circuit is minimized. The resonator is fabricated in the SMIC 0.25μm mixed signal CMOS process,the core area of the circuit is 0.09mm2. Tested results shown that at sampling frequency of 100MHz,for a 1kHz bandwith signal,the circuit achieves a SFDR of 77dB at resonance frequency of 25MHz,with the static power dissipation being only 10.5mW.
出处
《微电子学与计算机》
CSCD
北大核心
2010年第5期185-188,共4页
Microelectronics & Computer
基金
陕西省自然科学基金(2006F13)
