摘要
提出一款新型高精度、大量程TDC(时间数字转换)IP核的系统级构架。采用基于门延时的精细计数与基于时钟的粗计数相结合的技术模式获得高精度、大量程的测控指标。在使用底层编辑器对影响TDC精度的环形延时链(RDL)进行仔细的手动布局得到相对布局宏(RPM)之后,完成了系统级建模、Verilog系统级设计、仿真及验证。最后,在Xilinx FPGA开发板Spartan 3E XC3S500E环境下实现并完成了系统级验证。验证结果表明:分辨率可达2.5 ns.通过仿真和测试显示,其精度与现有TDC精度相比,提高了70%,量程达到8 ms,计数结果稳定准确。
A new time-to-digital converter with high precision and large range was presented. Fine-counter based on gate delay combined with coarse-counter based on clock was utilized for the sake of high precision and large test index. After getting RPM through placing ring delay line with FPGA editor in manual which effect the precision of TDC, system modeling, Verilog design, simulation and verification were implemented one after another. The system verification under Spartan 3E XC3S500E of Xilinx FP- GA development board was carried out. The results indicate that the resolution can reach 2. 5 ns with precision enhanced by 70% , and range reach 8 ms, furthermore the stabilization and exactness of count results.
出处
《仪表技术与传感器》
CSCD
北大核心
2010年第3期75-77,共3页
Instrument Technique and Sensor
