摘要
提出了一种基于Boonsobhak结构但电源效率更高的开关电流比较器。比较器采用主从式结构,工作模式由两相不交叠时钟控制。主比较器根据输入电流信号的极性产生微小电压差,同时将输出信号对输入信号的影响隔离开来。从比较器将主比较器产生的微小电压差进行再生放大,最终产生比较结果。提出的新比较器结构采用静态甲乙类锁存式比较器作为主比较器,以静态功耗为零的动态锁存式比较器为从比较器,使得整体比较器在保持较高速度的同时,功耗大为降低。采用CSMC0.6μmCMOS工艺设计并实现,实际测试结果显示开关电流比较器具有6.5bit分辨率,能在20MHz时钟频率下正常工作,而功耗降低了75%。
A power efficiency improved switched current eomparator based on Boonsobhak＇s comparator is presented. Controlled by two complementary clock signals, the proposed eomparator operates in a master and slave manner. The master comparator not only generates a voltage difference according to the input current, but also isolates the input terminal from the output signals to prevent extreme voltage surge, or kickback noise, while the slave comparator is allowed to regenerate and produce a valid digital output. Employing a static class AB latched comparator as the master comparator and a 0-static-power-dissipated dynamic latched eomparator as the slave one, the proposed current eomparator achieves high power efficiency and high speed. Designed and simulated in CSMC 0.6μm CMOS technology with 5 V supply voltage, the measurements show that the proposed SI comparator achieves a resolution of 6.5 bits, and works well at 20 MHz sampling frequency with 75% power reduction compared to the original.
出处
《固体电子学研究与进展》
CAS
CSCD
北大核心
2009年第4期579-583,共5页
Research & Progress of SSE
关键词
开关电流
比较器
甲乙类
高电源效率
switched current
comparator
class AB
power efficient
