摘要
采用SMIC0.18μmCMOS工艺设计了一个具有时钟提取及倍频功能的5Gb/s全速率2:1复接电路。整个电路由两部分构成,即:全速率2:1复接器和时钟提取及倍频环路。其中,后者从一路2.5Gb/s输入数据中提取出时钟信号,并为前者提供所需的2.5GHz及5GHz的时钟。Pottb覿cker鉴频鉴相器被运用以提高环路的捕获带宽。设计广泛采用了具有速度高和抗干扰能力强等诸多优点的电流模逻辑。仿真结果表明,本电路无需任何参考时钟,无需外接元件及手动相位调整或辅助捕获,就能可靠地工作在2.4～2.9Gb/s的输入数据速率上。芯片面积为812μm×675μm。电源电压1.8V时,功耗为162mW。
A 5-Gb/s full-rate 2：1 multiplexer with an on-chip integrated clock extraction circuit with frequency multiplication has been designed and fabricated in SMIC 0.18 μ m CMOS process. The whole circuit is composed of two parts： a full-rate 2：1 multiplexer and a clock extraction circuit with frequency multiplication. The later circuit extracts the clock signal from one of the input data signals, and provides 2.5GHz and 5GHz clock signals required by the former circuit. The Pottbacker phase frequency detector is used to wider the loop captureing bandwidth. The current mode logic is widely used for its advantages such as high speed and reduced time jitter and crosstalk. The simulation results show that the circuit can work reliably at any input data rate between 2.4 and 2.9 Gb/s with no need for external components, reference clock, or phase alignment between data and clock. The chip area is 812μ m × 675 μ m. At a single supply voltage of 1.8 V, the total power consumption is 162 mW .
出处
《中国集成电路》
2009年第12期20-24,共5页
China lntegrated Circuit
关键词
复接器
时钟提取
倍频
鉴频鉴相器
压控振荡器
multiplexer
clock extraction
frequency oscillator multiplication
phase frequency detector
voltage-controlled
