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基于VHDL的一种改进型数字锁相环的设计与实现 被引量:1

Design and Implementation of An Improved Digital Phase Locked Loop Based on VHDL
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摘要 研究了一种用估计周期值来调整计数器和控制器的改进型数字锁相环的实现方案。介绍了改进型数字锁相环的原理,详细分析各组成部分的性能,最后给出基于VHDL语言的实现过程。仿真结果表明,设计的锁相环具有宽频带、大相差、捕获时间短、性能稳定的特点。 An implementation scheme of an modified digital phase locked loop (DPLL) is studied by way of adjusting counter and controller with evaluated period value. Principle of the modified DPLL is introduced; performance of each component is analyzed in detail; and implementation scheme based on VHDL is presented. Simulation results show that the improved DPLL features wide frequency range, great phase difference, short capture time and stable performance.
出处 《火控雷达技术》 2009年第1期90-92,共3页 Fire Control Radar Technology
关键词 DPLL 数字鉴相器 捕获带宽 锁定时间 DPLL digital phase discriminator capture bandwidth locking time
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参考文献7

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二级参考文献4

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