摘要
采用有限元方法,建立了功率器件封装的三维有限元模型,分析了封装体的温度场和应力场,讨论了芯片粘贴焊层厚度、空洞等因数对大功率器件封装温度场和应力场的影响。有限元结果表明,封装体的最高温度为73.45℃,位于芯片的上端表面,焊层热应力最大值为171MPa,出现在芯片顶角的下面位置。拐角空洞对芯片最高温度影响最大,其次是中心空洞。空洞沿着对角线从中点移动到端点,芯片最高温度先减小后增加。焊层最大热应力出现在拐角空洞处,最大值为309MPa。最后分析了芯片粘贴工艺中空洞形成的机理,并根据有限元分析结论对工艺的改善优化提出建议。
A 3D FEA model of high power devices packaging was constructed by finite element analysis （FEA）. Effects of solder thickness of the die attachment and voiding on temperature and stress distribution of the model were discussed. The results show that the maximum temperature of 73.45 ℃ is on the top of chip and the maximum stress of 171 MPa in solder layer is under the chip comer. Corner void has the most severe influence on chip temperature distribution, and subsequently the center void. If the void location moved from center point of the chip diagonal line to edge point, the highest temperature of the chip decreases firstly, and then increases. The maximum thermal stress 309 MPa in solder layer is in the comer void. The formation mechanism of void was discussed, and some suggestions based on the FEA results for die attachment process were proposed.
出处
《半导体技术》
CAS
CSCD
北大核心
2009年第10期960-964,1031,共6页
Semiconductor Technology
基金
广东省自然科学基金(8151064101000014)
关键词
芯片粘贴
空洞
温度场
热应力
有限元分析
die attachment
voiding
temperature field
thermal stress
finite element analysis
