摘要
采用球栅阵列芯片尺寸封装技术和倒装芯片(Flip Chip,FC)技术构建了半桥集成电力电子模块(Integrated Power Electronics Module,IPEM),半桥FC-IPEM实现三维封装结构。采用阻抗测量法提取模块寄生电感和寄生电容,建立模块的寄生参数模型,对模块进行电气性能测试。结果表明:半桥FC-IPEM构成的同步整流Buck变换器输出滤波电感中的电流波动幅度小于0.6A。
A half bridge integrated power electronics module using flip chip technology （HB FC-IPEM） and ball grid array chip scale package technology was constituted. In the HB FC-IPEM, three-dimensional package structure was accomplished. Impedance measurement was used to extract the parasitic inductances and capacitances for building the parasitic parameter model of the HB FC-IPEM. Electrical performance of the module was tested. Results show that the current waving amplitude of synchronous rectification Buck converter output filter inductor constituted by HB FC-1PEM is less than 0.6 A.
出处
《电子元件与材料》
CAS
CSCD
北大核心
2009年第6期49-52,59,共5页
Electronic Components And Materials
基金
霍英东教育基金会高等院校青年教师基金资助项目(No.91058)
关键词
集成电力电子模块
倒装芯片技术
寄生参数模型
integrated power electronics module
flip chip technology
parasitic parameter module
