摘要
设计并采用FPGA技术高速实现了IDEA加密算法。根据IDEA算法原理和加解密速度要求,设计了密码芯片的内部模块;并对直接影响加解密速度的模乘运算,提出了一种倒金字塔形累加和动态补偿的模乘结构,利用FPGA技术高速实现了IDEA密码算法。仿真结果表明,采用试模乘结构的IDEA密码芯片能显著提高最大支持系统时钟频率和加解密速率,在33.3 MHz的时钟频率下的加解密速率可达到41.02 Mb/s。
A design and an implementation of a high performance International Data Encryption Algorithm (IDEA)are described in this paper.According to the principle of IDEA and requirement of encryption rate,the inner module of the crypto chip is designed.As the mo-mul operation directly impacts on the en/decryption rate,a new architecture for the mo-mul based on additive shape of inverse pyramid and dynamic compensator is presented. An implementation of a high performance IDEA based on FPGA is described in this paper.Results from the synthesis and simulations indicate that the IDEA crypto chip with the presented architecture can significantly improve system clock rate and encryption rate.41.02 Mb/s en/decryption rate under 33.3 MHz clock rate is achieved.
出处
《电子科技大学学报》
EI
CAS
CSCD
北大核心
2007年第S2期1125-1128,共4页
Journal of University of Electronic Science and Technology of China
基金
国家自然科学基金(60272091
60373109)
关键词
现场可编程门阵列
国际数据加密算法
模乘
FPGA
international data encryption algorithm
modulo multiplication
