摘要
采用FPGA技术,实现了IDEA算法,重点介绍了其关键功能模块的设计实现。根据IDEA密钥扩展方式和加解密流程,对IDEA的功能模块进行了划分和设计。其中,对复杂度较高而又不要求实时高速的模乘逆运算,进行了耗时分析;而对直接影响加解密速度的模乘运算,提出了一种新的模乘结构。
International Data Encryption Algorithm (IDEA) is implemented using FPGA. Design of main functional modules is described, which are partitioned based on the key expansion and the encryption/decryption flow of IDEA. For modulo-multiplication-inverse operation, which is highly complicated and does not require real-time and high speed, a time-consumption analysis is performed, and for modulo-multiplication operation, which has direct effects on the encryption/decryption rate, a new architecture is proposed.
出处
《微电子学》
CAS
CSCD
北大核心
2005年第2期206-209,共4页
Microelectronics
基金
国家自然科学基金资助项目(60272091
60373109)
