摘要
数字下变频器是宽带数字接收机的关键组成部分,由于其混频和滤波的速率很高,因而很难基于经典的结构实现。为了有效降低数字下变频器中的乘法速率,在多相滤波的基础上,提出了3种宽带数字下变频器结构,分别是混频器后置结构、最小公倍数结构和二次变频结构。详细分析了它们的设计原理和关键参数的选取方法。当抽取率为D时,将混频和滤波的乘法速率降为采样率的1/D。设计实例和仿真结果证明这3种结构是有效的。采用FPGA分别实现了3种宽带数字下变频器,评估了其硬件资源消耗情况,二次变频结构具有最高的实现效率。
Digital down convener is the key component of wideband digital receiver, it is hard to be implemented based on typical DDC structure due to its high operation rates of mixing and filtering. In order to reduce multiplicative operation rates effectively, three DDC structures based on poly-phase filter have been presented in this paper, which are called respectively the postpositional mixer structure, the least common multiple structure and the double frequency conversion structure. Design principles and methods for choosing the key parameters have been analyzed in detail. When decimating factor is D, the three DDC structures can reduce multiplication rates to one Dth of the sampling rate. Design examples and computer simulation results verify the feasibility of the three structures. Besides, the three DDC structures have been implemented using FPGA and the consumed logic resources for each structure have been evaluated as well, which proves that the double frequency conversion structure is the optimum among the three.
出处
《电子测量与仪器学报》
CSCD
2008年第5期43-47,共5页
Journal of Electronic Measurement and Instrumentation
关键词
数字下变频
多相滤波
实现结构
混频器后置
最小公倍数
二次变频
digital down-conversion, poly-phase filtering, implemental structure, postpositional mixer, least common multiple, double frequency conversion.
