摘要
设计了一个用于40 MHz采样率,12位精度流水线A/D转换器第一级的MDAC电路。该电路采用高增益带宽积的增益自举放大器,在3.5pF负载电容下,可以在8ns内稳定在最终值的0.01%;设计了低失调、低回踢噪声比较器。蒙特卡罗分析表明,失调电压小于7mV。电路采用SMIC0.35μm/3.3V CMOS工艺,用于一个带数字校正的流水线A/D转换器。在MDAC中加入一个D/A接口电路,可以在不引入过多模拟电路的前提下,配合数字校正部分完成其校正功能。
An MDAC used for the first stage of a 40 MS/s 12-bit pipelined A/D converter was presented. The circuit was constructed with a high GBW gain-boosted telescopic cascade amplifier, which could settle at 0. 01% in 8 ns. A low-offset and low kickback noise comparator was designed. Monte Carlo analysis showed that the circuit had an offset below 7 inV. Simulated in SMIC＇s 0. 35 μm/3.3 V CMOS process, the MDAC was used in a pipelined A/ D converter with digital calibration. A digital-to-analog interface was also designed, which could help fulfilling digital calibration without introducing many additional analog circuits.
出处
《微电子学》
CAS
CSCD
北大核心
2008年第5期614-617,共4页
Microelectronics
