摘要
数字信号处理常常包含大量数据运算,这使得数据Cache成为影响其性能的关键因素。特别是对于我们研制的双簇VLIW结构YHFT DSP系列处理器,Cache的失效会导致整个内核八条流水线同时停顿。所以,减小Cache失效延迟能给处理器性能带来显著的提升。本文研究的主要问题是如何针对一级数据Cache的读失效操作进行优化,从四个方面进行,分别为提前发读请求、请求字优先、合并并行失效读和后台处理Snooping。模拟结果表明,采用这些优化措施后,处理器的性能提高了8.36%。
In digital signal processors, the data cache is a key element. It is important for the designer to consider how to reduce the overhead caused by cache miss. Especially in the dual cluster VLIW DSP that we have developed, the cache miss will stall all 8 pipelines in the kernel. So an optimization design of the data cache will get a great performance improvement. In this paper, we present four techniques for optimizing the data cache： early read request, request word first, merging two parallel read misses, and background processing snooping. The simulation results show that these methods can improve the processor ＇s performance by 8. 36 %.
出处
《计算机工程与科学》
CSCD
2008年第9期119-121,125,共4页
Computer Engineering & Science
基金
国家自然科学基金资助项目(60473079)
教育部高等学校博士学科点专项科研基金资助项目(20059998026)
