摘要
除运算采用泰勒级数展开,用5级流水线结构,查找表大小缩小为2.5kB,并获得固定延迟.FPGA综合结果表明,与其他设计电路相比,面积减小了33%.
In this paper, we propose a fixed latency pipelined divider using mcdified Taylor-series expansion for floating point operations. The divider has 5 stages pipeline and its ROM only 2.5kB. Synthesize on FPGA, the proposed divider reduces chip area by about 33% than the other pipelined divider.
出处
《微电子学与计算机》
CSCD
北大核心
2008年第5期84-87,共4页
Microelectronics & Computer
基金
安徽省自然科学研究项目(KJ2007B3442C)
关键词
浮点
除法
泰勒级数
FPGA
floating point
divide
Taylor-series
FPGA
