摘要
通过分布式语音识别DSR的研究,提出了基于FPGA平台的前端处理系统结构。对其中两个除法器分别采用了LUT查找表和常数除法器的结构。用VerilogHDL语言进行建模仿真,并与Matlab的建模结果进行了对比。结果表明,与之前的方法相比,系统能够在较短的时钟周期内计算出LPCC系数,节省了大量的运算时间和一定的面积。
According to the research of distributed speech recognition （DSR）,this paper introduces a front-end processing system,which is based on the FPGA. Especially, the system adopts LUT （look_up table） divider and constant divider. Finally, after comparing the system simulation with the result of Matlab modeling, the system could compute LPCC coefficient in shorter clock cycle. The experiment results show that comparing with the method used previously, this method saves numbers of operation time and some areas in the chip.
出处
《电子技术应用》
北大核心
2010年第2期40-43,共4页
Application of Electronic Technique
