摘要
研究了一种用于微处理器时钟同步PLL的高带宽低噪声的压控振荡器（VCO），该VCO采用了交叉耦合的电流饥饿型环形振荡器，通过改善其控制电压变换电路，大大拓宽了压控增益的线性范围，消除了振荡器对控制电压的影响，降低了输出时钟的相位噪声。基于CSMC 3．3V0．35μm CMOS工艺的仿真结果表明，取延迟单元沟道长度为1μm、中心频率为365MHz时，压控增益为300MHz／V，其线性区覆盖范围是30～700MHz，在偏离中心频率600kHz处的相位噪声为-95dB／Hz，低频1／f噪声在-20dB／Hz以下。该VCO可以通过适当减小延迟单元沟道长度来拓宽压控增益线性范围。
A wide-bandwidth, low-noise VCO used in microprocessor PLL synchronizer was investigated, including a cross-coupled current-steering ring oscillator. By improving the performance of the control-vohagetransformed circuit, the linear range of the VCO gain is enlarged, the influence of oscillator to control-voltage is eliminated, and the phase noise of output clock is decreased. The simulation is achieved with CSMC 3.3 V, 0.35/μm, CMOS process. When choosing 1 /μm for the channel length of the delay cell and 365 MHz for the center frequency, the results reveal that the gain is 300 MHz/V, the linear range is 30 - 700 MHz, the phase noise is - 95 dB/Hz at 600 kHz offset from center frequency, and the low frequency 1/f noise is below -20 dB/Hz. The linear range of the VCO gain can be enlarged by properly decreasing the channel length of the delay cell.
出处
《半导体技术》
CAS
CSCD
北大核心
2007年第12期1073-1076,共4页
Semiconductor Technology
