摘要
装箱是FPGA工艺映射中的最后一步流程。该文提出了一种全新的对FPGA可编程逻辑块进行功能级建模的方法,并给出了基于此建模的通用性装箱算法FDUPack。实验中应用该建模方法对几种不同类型的FPGA的逻辑块进行建模,并使用装箱算法将大量的测试电路装箱到这些不同的逻辑块中,经过与已有的针对某一特定结构的装箱算法比较,该算法体现了很好的通用性。
Logic block packing is the last procedure of FPGA technology mapping. A novel function level modeling method for programmable logic block is proposed. Based on this modeling, a universal logic block packing algorithm FDUPack is presented. In the experiment some logic blocks of different types of FPGAs are modeled, and by using the packing algorithm a lot of benchmarks are packed to these different types of logic blocks. Compared with the existent logic block specific packing algorithms, FDUPack is structure-independent and universal.
出处
《计算机工程》
CAS
CSCD
北大核心
2007年第6期239-241,244,共4页
Computer Engineering
基金
上海应用材料科技合作共同计划(AM0406)
国家自然科学基金资助项目(60076014)
关键词
工艺映射
装箱算法
建模
现场可编程门阵列
Technology mapping
Packing algorithm
Modeling
Field programmable gate array
