摘要
介绍了基于现场可编程门阵列(FPGA)技术的用于1553B通信网络的多路总线接口板(MBI板)的总体设计方案,通过它可实现总线与子系统之间的通信,同时就设计中常遇到的三个问题:时钟延时,时钟偏移,同步器的亚稳态性加以说明且提出了解决方法,并搭建了用于1553B通信网络的多路总线测试平台来对MBI板进行调试。
The 1553B Muhibus Interface based on FPGA is designed, the communication between the bus and the subsystem is realized. After analyzing the clock delay, the clock skew and the critical steady synchronizer which are difficult in the design, some settlement methods are introduced. Also, the 1553B Muhibus Interface test platform are built.
出处
《计算机测量与控制》
CSCD
2007年第4期501-502,530,共3页
Computer Measurement &Control
