摘要
论述了利用Verilog HDL语言实现ISA端口操作和脉冲驱动RAM接口逻辑设计,并充分利用端口读操作脉冲的所有信息(前后沿和其低电平)实现了微机-端口-RAM的流水线式接口设计,设计原理及其编程简洁,基于可编程逻辑器件FPGA的逻辑实现使外部硬件连接布线简单可靠;逻辑仿真结果符合硬件接口时序的要求,在线阵CCD数据采集系统中应用效果良好。
The ISA port read ＆. write and pulse driving RAM interface are designed in FPGA by Verilog HDL. The read pulse information, including two edges and low level, is used in the computer-port - RAM pipeline interface design. The principle and its programming are rather simple, and integrating the logic in a FPGA device makes the outside board routing more orderly and more reliable. The logic simulation results meet all the re quirements of the hardware interface timing, thus the design operates successfully in the CCD data acquisition system.
出处
《计算机测量与控制》
CSCD
2005年第12期1394-1395,1399,共3页
Computer Measurement &Control
基金
国家自然科学基金资助课题(69774029)
