摘要
介绍了使用VHDL描述有限状态机的方法,重点分析了综合过程中的竞争和毛刺现象产生的原因,并提供了解决方法。最后以图形学中的直线算法为例实现了可综合的FSM描述,并通过门级仿真验证了其正确性。
The method of description of finite state machine with VHDL is presented.This paper analyses causes of the phenomena of burr and competition in the process of synthesis in detail and provides the solutions.At the end,it imple-ments a synthetical straight line algorithm of graphics with FSM,and the function of it is proved to be correct through logic simulation.
出处
《计算机工程与应用》
CSCD
北大核心
2005年第6期111-113,共3页
Computer Engineering and Applications
基金
部委预研项目
