摘要
介绍了补码阵列乘法器的Pezaris算法。为提高运算速度,利用流水线技术进行改进,设计出流水线结构阵列乘法器,使用VHDL语言建模,在Quartus II集成开发环境下进行仿真和功能验证。
The Pezaris algorithm of complement Array Multiplier has been introduced. For speeding up , it has been improved with the technique of pipeline. A N×N pipeline Array Multiplier has been designed with VHDL . The conclusion of Simulation and func- tion verification for it in the integration development environment of Quartus II has been given.
出处
《微计算机信息》
北大核心
2007年第23期303-304,276,共3页
Control & Automation
基金
江苏省高新技术产业发展项目(JH03-018)
