摘要
针对流水线结构阵列乘法器,分别采用寄存器翻转统计和门级翻转率统计的方法进行了功耗分析,创新地提出了一种通过增加判断逻辑进行数据预分流以实现功耗优化的方法。实验结果证明,这种优化方法能够带来明显的功耗节省。类似方法也可普遍用于逻辑行为对称但实现结构不对称的数据通路单元的低功耗设计实现中。
A method of pre-distributing the calculated data by some additional judge logics is presented to optimize the power consumption of a pipelined array multiplier.Results from the experiment are compared by gate-level simulation and register-annotated methods.It has been shown that this simple method of optimization is effective in decreasing the power consumption of the circuit.So,it can be widely used in the implementation of low-power design of other data-path modules with asymmetric architectures and symmetric logic behaviors.
出处
《微电子学》
CAS
CSCD
北大核心
2004年第1期34-37,共4页
Microelectronics
基金
国家自然科学基金资助项目(59995550-1)
清华大学985关键研究基金资助项目
