We use an electro-thermal coupled Monte Carlo simulation framework to investigate the self-heating effect(SHE) in 14 nm bulk n Fin FETs with ambient temperature(TA) from 220 to 400 K. Based on this method, nonloca...We use an electro-thermal coupled Monte Carlo simulation framework to investigate the self-heating effect(SHE) in 14 nm bulk n Fin FETs with ambient temperature(TA) from 220 to 400 K. Based on this method, nonlocal heat generation can be achieved. Contact thermal resistances of Si/Metal and Si/Si O_2 are selected to ensure that the source and drain heat dissipation paths are the first two heat dissipation paths. The results are listed below:(i) not all input power(Q_(input) turns into heat generation in the device region and some is taken out by the thermal non-equilibrium carriers, owing to the serious non-equilibrium transport;(ii) a higher TA leads to a larger ratio of input power turning into heat generation in the device region at the same operating voltages;(iii) SHE can lead to serious degradation in the carrier transport, which will increase when TA increases;(iv) the current degradation can be 8.9% when Vds = 0.7 V, Vgs = 1 V and TA = 400 K;(v) device thermal resistance(Rth) increases with increasing of TA, which is seriously impacted by the non-equilibrium transport. Hence, the impact of TA should be carefully considered when investigating SHE in nanoscale devices.展开更多
本文提出了一个新型的SOI埋层结构SOANN(silicon on aluminum nitride with nothing),用AIN代替传统的SiO2材料,并在SOI埋氧化层中引入空洞散热通道.分析了新结构SOI器件的自加热效应.研究结果表明:用AIN做为SOI埋氧化层的材料,降低了...本文提出了一个新型的SOI埋层结构SOANN(silicon on aluminum nitride with nothing),用AIN代替传统的SiO2材料,并在SOI埋氧化层中引入空洞散热通道.分析了新结构SOI器件的自加热效应.研究结果表明:用AIN做为SOI埋氧化层的材料,降低了晶格温度,有效抑制了自加热效应.埋氧化层中的空洞,可以进一步提供散热通道,使埋氧化层的介电常数下降,减小了电力线从漏端通过埋氧到源端的耦合,有效抑制了漏致势垒降低DIBL(drain Induced barrier lowering)效应.因此,本文提出的新型SOANN结构可以提高SOI器件的整体性能,具有优良的可靠性.展开更多
The motion of current filaments in avalanching PIN diodes has been investigated in this paper by 2D transient numerical simulations. The simulation results show that the filament can move along the length of the PIN d...The motion of current filaments in avalanching PIN diodes has been investigated in this paper by 2D transient numerical simulations. The simulation results show that the filament can move along the length of the PIN diode back and forth when the self-heating effect is considered. The voltage waveform varies periodically due to the motion of the filament. The filament motion is driven by the temperature gradient in the filament due to the negative temperature dependence of the impact ionization rates. Contrary to the traditional understanding that current filamentation is a potential cause of thermal destruction, it is shown in this paper that the thermally-driven motion of current filaments leads to the homogenization of temperature in the diode and is expected to have a positive influence on the failure threshold of the PIN diode.展开更多
重掺杂使导带、价带带边同时发生了收缩 ,从而产生能带变窄效应 ( BGN)。对于因重掺杂 NPN突变 Al Ga As/Ga As HBT,而引起 BGN导带和价带突变界面势垒形状及高度都发生改变结果 ,以致对电流输出特性产生重要的影响。本文基于 Jain-Roul...重掺杂使导带、价带带边同时发生了收缩 ,从而产生能带变窄效应 ( BGN)。对于因重掺杂 NPN突变 Al Ga As/Ga As HBT,而引起 BGN导带和价带突变界面势垒形状及高度都发生改变结果 ,以致对电流输出特性产生重要的影响。本文基于 Jain-Roulston禁带收缩模型及热场发射——扩散载流子输运机制 ,对考虑自热效应下的重掺杂 Al Ga As/Ga-As HBT电流特性进行了深入的研究。通过与其它计算程序常用的几种 BGN模型比较得出 :为了更好描述电流传输 ,利用 Jain-Roulston的 BGN模型 ,考虑导带。展开更多
在集成电路设计领域,绝缘体上硅(SOI)工艺以其较小的寄生效应、更快的速度,得到广泛应用。但由于SOI工艺器件的结构特点及自加热效应(SHE)的影响,其静电放电(ESD)防护器件设计成为一大技术难点。当工艺进入深亚微米技术节点,基于部分耗...在集成电路设计领域,绝缘体上硅(SOI)工艺以其较小的寄生效应、更快的速度,得到广泛应用。但由于SOI工艺器件的结构特点及自加热效应(SHE)的影响,其静电放电(ESD)防护器件设计成为一大技术难点。当工艺进入深亚微米技术节点,基于部分耗尽型SOI(PD-SOI)工艺的ESD防护器件设计尤为困难。为了提高深亚微米SOI工艺电路的可靠性,开展了分析研究。结合SOI工艺器件的结构特点,针对性地进行了ESD防护器件选择,合理设计了器件尺寸参数,并优化设计了器件版图。使用该设计的一款数字电路,通过了4.5 k V人体模型(HBM)的ESD测试。该设计有效解决了深亚微米SOI工艺ESD防护器件稳健性弱的问题。展开更多
研究了在大功率工作条件下的Ga N HFET器件的自加热效应。当Ga N HFET器件工作在大功率条件下时所产生的自加热效应,将会使得器件的有源沟道层的温度升高,影响到器件的工作特性。首先分析了多栅指结构的Ga N HFET器件在一定功耗条件下...研究了在大功率工作条件下的Ga N HFET器件的自加热效应。当Ga N HFET器件工作在大功率条件下时所产生的自加热效应,将会使得器件的有源沟道层的温度升高,影响到器件的工作特性。首先分析了多栅指结构的Ga N HFET器件在一定功耗条件下的的温度分布情况,然后在此基础之上,对Ga N HFET做了相应的优化,使得器件的温度有一定程度的降低。展开更多
The evaluation of thermal resistance constitution for packaged A1GaN/GaN high electron mobility transistor (HEMT) by structure function method is proposed in this paper. The evaluation is based on the transient heat...The evaluation of thermal resistance constitution for packaged A1GaN/GaN high electron mobility transistor (HEMT) by structure function method is proposed in this paper. The evaluation is based on the transient heating measurement of the A1GaN/GaN HEMT by pulsed electrical temperature sensitive parameter method. The extracted chip-level and package-level thermal resistances of the packaged multi-finger A1GaN/GaN HEMT with 400μm SiC substrate are 22.5 K/W and 7.2 K/W respectively, which provides a non-invasive method to evaluate the chip-level thermal resistance of packaged A1GaN/GaN HEMTs. It is also experimentally proved that the extraction of the chip- level thermal resistance by this proposed method is not influenced by package form of the tested device and temperature boundary condition of measurement stage.展开更多
基金supported by the National Key Technology Research and Development Program of China(No.2016YFA0202101)the National Natural Science Foundation of China(Nos.61421005,61604005)+1 种基金the National High-Tech R&D Program(863 Program)(No.2015AA016501)The simulation was carried out at National Supercomputer Center in Tianjin,with Tian He-1(A)
文摘We use an electro-thermal coupled Monte Carlo simulation framework to investigate the self-heating effect(SHE) in 14 nm bulk n Fin FETs with ambient temperature(TA) from 220 to 400 K. Based on this method, nonlocal heat generation can be achieved. Contact thermal resistances of Si/Metal and Si/Si O_2 are selected to ensure that the source and drain heat dissipation paths are the first two heat dissipation paths. The results are listed below:(i) not all input power(Q_(input) turns into heat generation in the device region and some is taken out by the thermal non-equilibrium carriers, owing to the serious non-equilibrium transport;(ii) a higher TA leads to a larger ratio of input power turning into heat generation in the device region at the same operating voltages;(iii) SHE can lead to serious degradation in the carrier transport, which will increase when TA increases;(iv) the current degradation can be 8.9% when Vds = 0.7 V, Vgs = 1 V and TA = 400 K;(v) device thermal resistance(Rth) increases with increasing of TA, which is seriously impacted by the non-equilibrium transport. Hence, the impact of TA should be carefully considered when investigating SHE in nanoscale devices.
文摘本文提出了一个新型的SOI埋层结构SOANN(silicon on aluminum nitride with nothing),用AIN代替传统的SiO2材料,并在SOI埋氧化层中引入空洞散热通道.分析了新结构SOI器件的自加热效应.研究结果表明:用AIN做为SOI埋氧化层的材料,降低了晶格温度,有效抑制了自加热效应.埋氧化层中的空洞,可以进一步提供散热通道,使埋氧化层的介电常数下降,减小了电力线从漏端通过埋氧到源端的耦合,有效抑制了漏致势垒降低DIBL(drain Induced barrier lowering)效应.因此,本文提出的新型SOANN结构可以提高SOI器件的整体性能,具有优良的可靠性.
基金Project supported by the National Natural Science Foundation of China(No.60776034)
文摘The motion of current filaments in avalanching PIN diodes has been investigated in this paper by 2D transient numerical simulations. The simulation results show that the filament can move along the length of the PIN diode back and forth when the self-heating effect is considered. The voltage waveform varies periodically due to the motion of the filament. The filament motion is driven by the temperature gradient in the filament due to the negative temperature dependence of the impact ionization rates. Contrary to the traditional understanding that current filamentation is a potential cause of thermal destruction, it is shown in this paper that the thermally-driven motion of current filaments leads to the homogenization of temperature in the diode and is expected to have a positive influence on the failure threshold of the PIN diode.
文摘重掺杂使导带、价带带边同时发生了收缩 ,从而产生能带变窄效应 ( BGN)。对于因重掺杂 NPN突变 Al Ga As/Ga As HBT,而引起 BGN导带和价带突变界面势垒形状及高度都发生改变结果 ,以致对电流输出特性产生重要的影响。本文基于 Jain-Roulston禁带收缩模型及热场发射——扩散载流子输运机制 ,对考虑自热效应下的重掺杂 Al Ga As/Ga-As HBT电流特性进行了深入的研究。通过与其它计算程序常用的几种 BGN模型比较得出 :为了更好描述电流传输 ,利用 Jain-Roulston的 BGN模型 ,考虑导带。
文摘在集成电路设计领域,绝缘体上硅(SOI)工艺以其较小的寄生效应、更快的速度,得到广泛应用。但由于SOI工艺器件的结构特点及自加热效应(SHE)的影响,其静电放电(ESD)防护器件设计成为一大技术难点。当工艺进入深亚微米技术节点,基于部分耗尽型SOI(PD-SOI)工艺的ESD防护器件设计尤为困难。为了提高深亚微米SOI工艺电路的可靠性,开展了分析研究。结合SOI工艺器件的结构特点,针对性地进行了ESD防护器件选择,合理设计了器件尺寸参数,并优化设计了器件版图。使用该设计的一款数字电路,通过了4.5 k V人体模型(HBM)的ESD测试。该设计有效解决了深亚微米SOI工艺ESD防护器件稳健性弱的问题。
文摘研究了在大功率工作条件下的Ga N HFET器件的自加热效应。当Ga N HFET器件工作在大功率条件下时所产生的自加热效应,将会使得器件的有源沟道层的温度升高,影响到器件的工作特性。首先分析了多栅指结构的Ga N HFET器件在一定功耗条件下的的温度分布情况,然后在此基础之上,对Ga N HFET做了相应的优化,使得器件的温度有一定程度的降低。
基金supported by the Natural Science Foundation of Beijing,China (Grant No. 4092005)the National High Technology Research and Development Program of China (Grant No. 2009AA032704)the Specialized Research Fund for the Doctoral Program of Higher Education of China (Grant No. 20091103110006)
文摘The evaluation of thermal resistance constitution for packaged A1GaN/GaN high electron mobility transistor (HEMT) by structure function method is proposed in this paper. The evaluation is based on the transient heating measurement of the A1GaN/GaN HEMT by pulsed electrical temperature sensitive parameter method. The extracted chip-level and package-level thermal resistances of the packaged multi-finger A1GaN/GaN HEMT with 400μm SiC substrate are 22.5 K/W and 7.2 K/W respectively, which provides a non-invasive method to evaluate the chip-level thermal resistance of packaged A1GaN/GaN HEMTs. It is also experimentally proved that the extraction of the chip- level thermal resistance by this proposed method is not influenced by package form of the tested device and temperature boundary condition of measurement stage.