Contrary to general understanding, a test result shows that devices with a shorter channel length have a degraded ESD performance in the advanced silicided CMOS process. Such a phenomenon in a gate-grounded NMOSFET （...Contrary to general understanding, a test result shows that devices with a shorter channel length have a degraded ESD performance in the advanced silicided CMOS process. Such a phenomenon in a gate-grounded NMOSFET （GGNMOS） was investigated, and the current spreading effect was verified as the predominant factor. Due to transmission line pulse （TLP） measurements and Sentaurus technology computer aided design （TCAD） 2-D numerical simulations, parameters such as current gain, on-resistance and power density were discussed in detail.展开更多
Gate-grounded N-channel MOSFET(GGNMOS)has been extensively used for on-chip electrostatic discharge(ESD)protection.However,the ESD performance of the conventional GGNMOS is significantly degraded by the current crowdi...Gate-grounded N-channel MOSFET(GGNMOS)has been extensively used for on-chip electrostatic discharge(ESD)protection.However,the ESD performance of the conventional GGNMOS is significantly degraded by the current crowding effect.In this paper,an enhanced GGNMOS with P-base layer(PB-NMOS)are proposed to improve the ESD robustness in BCD process without the increase in layout area or additional layer.TCAD simulations are carried out to explain the underlying mechanisms of that utilizing the P-base layer can effectively restrain the current crowing effect in proposed devices.All devices are fabricated in a 0.5-μm BCD process and measured using the transmission line pulsing(TLP)tester.Compared with the conventional GGNMOS,the proposed PB-NMOS devices offer a higher failure current than its conventional counterpart,which can be increased by 15.38%.Furthermore,the PB-NMOS type 3 possesses a considerably lower trigger voltage than the conventional GGNMOS to protect core circuit effectively.展开更多
文摘当两个拥有不同电势的物体接触时,电势差会导致电荷流动,从而产生放电,这种现象称为静电放电(Electrostatic Discharge,ESD)。ESD所产生的瞬间高电压和大电流,会烧毁击穿半导体中的器件,最终导致整个半导体芯片永久性失效。随着硅基CMOS工艺技术的不断进步,由ESD引起的失效问题也随着特征尺寸的变小而日益严重。首先分析了几种常见的静电放电模式以及测试模型,随后基于SMIC公司0.18μm BCD工艺,在传统GGNMOS抗辐照ESD结构基础上进行优化,设计一款GGNMOS+RC Power Clamp抗ESD结构。经流片测试后,证明该款电路抗ESD能力强,且性能稳定。
文摘Contrary to general understanding, a test result shows that devices with a shorter channel length have a degraded ESD performance in the advanced silicided CMOS process. Such a phenomenon in a gate-grounded NMOSFET （GGNMOS） was investigated, and the current spreading effect was verified as the predominant factor. Due to transmission line pulse （TLP） measurements and Sentaurus technology computer aided design （TCAD） 2-D numerical simulations, parameters such as current gain, on-resistance and power density were discussed in detail.
文摘Gate-grounded N-channel MOSFET(GGNMOS)has been extensively used for on-chip electrostatic discharge(ESD)protection.However,the ESD performance of the conventional GGNMOS is significantly degraded by the current crowding effect.In this paper,an enhanced GGNMOS with P-base layer(PB-NMOS)are proposed to improve the ESD robustness in BCD process without the increase in layout area or additional layer.TCAD simulations are carried out to explain the underlying mechanisms of that utilizing the P-base layer can effectively restrain the current crowing effect in proposed devices.All devices are fabricated in a 0.5-μm BCD process and measured using the transmission line pulsing(TLP)tester.Compared with the conventional GGNMOS,the proposed PB-NMOS devices offer a higher failure current than its conventional counterpart,which can be increased by 15.38%.Furthermore,the PB-NMOS type 3 possesses a considerably lower trigger voltage than the conventional GGNMOS to protect core circuit effectively.
