A design of high dynamic range linear radio frequency power detector （PD）, aimed for transmitter carrier leakage suppression is presented in this paper. Based on the logarithmic amplifier principle, this detector ut...A design of high dynamic range linear radio frequency power detector （PD）, aimed for transmitter carrier leakage suppression is presented in this paper. Based on the logarithmic amplifier principle, this detector utilizes the successive detection method to achieve a high dynamic range in the radio frequency band. In order to increase sensitivity, a low noise amplifier （LNA） is placed in the front of this detector. DC coupling is adopted in this architecture to reduce parasitics and save area, but this will unavoidably cause DC offsets in the circuit which are detrimental to the dynamic range. So a DC offset cancelling （DCOC） technique is proposed to solve the problem. Finally, this detector was fabricated in the SMIC 0.13μm CMOS process. The measured results show that it achieves a wide dynamic range of 50 dB/40 dB with log errors in 4-1 dB at 900 MHz/2 GHz, while draws 16 mA from a 1.5 V power supply. The active chip area is 0.27×0.67 mm2.展开更多
A 3.125-Gb/s transimpedance amplifier（TIA） for an optical communication system is realized in 0.35μm CMOS technology.The proposed TIA employs a regulated cascode configuration as the input stage, and adopts DC-canc...A 3.125-Gb/s transimpedance amplifier（TIA） for an optical communication system is realized in 0.35μm CMOS technology.The proposed TIA employs a regulated cascode configuration as the input stage, and adopts DC-cancellation techniques to stabilize the DC operating point.In addition,noise optimization is processed. The on-wafer measurement results show the transimpedance gain of 54.2 dBΩand -3 dB bandwidth of 2.31 GHz.The measured average input referred noise current spectral density is about 18.8 pA/（？）.The measured eye diagram is clear and symmetrical for 2.5-Gb/s and 3.125-Gb/s PRBS.Under a single 3.3-V supply voltage,the TIA consumes only 58.08 mW,including 20 mW from the output buffer.The whole die area is 465×435μm^2.展开更多
A low-voltage, low-power, and high-gain rail-to-rail operational amplifier （OpAmp） is presented. The replica-amplifier gain enhancement technique is applied to improve the DC gain of the amplifier, which does not de...A low-voltage, low-power, and high-gain rail-to-rail operational amplifier （OpAmp） is presented. The replica-amplifier gain enhancement technique is applied to improve the DC gain of the amplifier, which does not degrade the output swing and is very suitable for low-voltage applications. In a 0. 18/μm standard CMOS process,a 1V OpAmp with rail-to-rail output is designed. For a load capacitance of 5 pF,simulation by HSPICE shows that this OpAmp achieves an effective open-loop DC gain of 65. 9dB,gain bandwidth of 70.28 MHz,and phase margin of 50 with a quiescent power dissipation of 156.7μW.展开更多
This paper describes a very low level dc current amplifier using switched capacitor (SC) circuit to miniaturize and improve its output response speed, instead of the conventionally used high-oh-mage resistor. A switch...This paper describes a very low level dc current amplifier using switched capacitor (SC) circuit to miniaturize and improve its output response speed, instead of the conventionally used high-oh-mage resistor. A switched capacitor filter (SCF) and an offset controller are also used to decrease vibrations and offset voltage at the output of the amplifier. The simulation results show that the parasitic capacitances that are distributed to the input portion of the amplifier have some effect on offset voltage. From the experimental results, it is seen that the duty ratio of the clock cycle of SC circuit should be in the range from 0.05 to 0.70. It is suggested that the proposed very low level dc current amplifier using SC circuit is an effective way to obtain both a faster output response and its miniaturization.展开更多
To miniaturize a very low level dc current amplifier and to improve its output response speed, the switched capacitor negative feedback circuit (SCNF), instead of the conventionally used high-ohmage resistor, is prese...To miniaturize a very low level dc current amplifier and to improve its output response speed, the switched capacitor negative feedback circuit (SCNF), instead of the conventionally used high-ohmage resistor, is presented in this paper. In our system, a switched capacitor filter (SCF) and an offset controller are also used to decrease vibrations and offset voltage at the output of the amplifier using SCNF. The theoretical output voltage of the very low level dc current amplifier using SCNF is obtained. The experimental results show that the unnecessary components of the amplifier’s output are much decreased, and that the response speed of the amplifier with both the SCNF and SCF is faster than that using high-ohmage resistor.展开更多
基金Project supported by the Important National Science & Technology Specific Projects,China(No.2010ZX03001-004)the National High Technology Research and Development Program of China(No.2009AA011605)
文摘A design of high dynamic range linear radio frequency power detector （PD）, aimed for transmitter carrier leakage suppression is presented in this paper. Based on the logarithmic amplifier principle, this detector utilizes the successive detection method to achieve a high dynamic range in the radio frequency band. In order to increase sensitivity, a low noise amplifier （LNA） is placed in the front of this detector. DC coupling is adopted in this architecture to reduce parasitics and save area, but this will unavoidably cause DC offsets in the circuit which are detrimental to the dynamic range. So a DC offset cancelling （DCOC） technique is proposed to solve the problem. Finally, this detector was fabricated in the SMIC 0.13μm CMOS process. The measured results show that it achieves a wide dynamic range of 50 dB/40 dB with log errors in 4-1 dB at 900 MHz/2 GHz, while draws 16 mA from a 1.5 V power supply. The active chip area is 0.27×0.67 mm2.
基金Project supported by the National High Technology Research and Development Program of China(No.2006AA012284)
文摘A 3.125-Gb/s transimpedance amplifier（TIA） for an optical communication system is realized in 0.35μm CMOS technology.The proposed TIA employs a regulated cascode configuration as the input stage, and adopts DC-cancellation techniques to stabilize the DC operating point.In addition,noise optimization is processed. The on-wafer measurement results show the transimpedance gain of 54.2 dBΩand -3 dB bandwidth of 2.31 GHz.The measured average input referred noise current spectral density is about 18.8 pA/（？）.The measured eye diagram is clear and symmetrical for 2.5-Gb/s and 3.125-Gb/s PRBS.Under a single 3.3-V supply voltage,the TIA consumes only 58.08 mW,including 20 mW from the output buffer.The whole die area is 465×435μm^2.
文摘A low-voltage, low-power, and high-gain rail-to-rail operational amplifier （OpAmp） is presented. The replica-amplifier gain enhancement technique is applied to improve the DC gain of the amplifier, which does not degrade the output swing and is very suitable for low-voltage applications. In a 0. 18/μm standard CMOS process,a 1V OpAmp with rail-to-rail output is designed. For a load capacitance of 5 pF,simulation by HSPICE shows that this OpAmp achieves an effective open-loop DC gain of 65. 9dB,gain bandwidth of 70.28 MHz,and phase margin of 50 with a quiescent power dissipation of 156.7μW.
文摘This paper describes a very low level dc current amplifier using switched capacitor (SC) circuit to miniaturize and improve its output response speed, instead of the conventionally used high-oh-mage resistor. A switched capacitor filter (SCF) and an offset controller are also used to decrease vibrations and offset voltage at the output of the amplifier. The simulation results show that the parasitic capacitances that are distributed to the input portion of the amplifier have some effect on offset voltage. From the experimental results, it is seen that the duty ratio of the clock cycle of SC circuit should be in the range from 0.05 to 0.70. It is suggested that the proposed very low level dc current amplifier using SC circuit is an effective way to obtain both a faster output response and its miniaturization.
文摘To miniaturize a very low level dc current amplifier and to improve its output response speed, the switched capacitor negative feedback circuit (SCNF), instead of the conventionally used high-ohmage resistor, is presented in this paper. In our system, a switched capacitor filter (SCF) and an offset controller are also used to decrease vibrations and offset voltage at the output of the amplifier using SCNF. The theoretical output voltage of the very low level dc current amplifier using SCNF is obtained. The experimental results show that the unnecessary components of the amplifier’s output are much decreased, and that the response speed of the amplifier with both the SCNF and SCF is faster than that using high-ohmage resistor.
