摘要
This paper describes a very low level dc current amplifier using switched capacitor (SC) circuit to miniaturize and improve its output response speed, instead of the conventionally used high-oh-mage resistor. A switched capacitor filter (SCF) and an offset controller are also used to decrease vibrations and offset voltage at the output of the amplifier. The simulation results show that the parasitic capacitances that are distributed to the input portion of the amplifier have some effect on offset voltage. From the experimental results, it is seen that the duty ratio of the clock cycle of SC circuit should be in the range from 0.05 to 0.70. It is suggested that the proposed very low level dc current amplifier using SC circuit is an effective way to obtain both a faster output response and its miniaturization.
This paper describes a very low level dc current amplifier using switched capacitor (SC) circuit to miniaturize and improve its output response speed, instead of the conventionally used high-oh-mage resistor. A switched capacitor filter (SCF) and an offset controller are also used to decrease vibrations and offset voltage at the output of the amplifier. The simulation results show that the parasitic capacitances that are distributed to the input portion of the amplifier have some effect on offset voltage. From the experimental results, it is seen that the duty ratio of the clock cycle of SC circuit should be in the range from 0.05 to 0.70. It is suggested that the proposed very low level dc current amplifier using SC circuit is an effective way to obtain both a faster output response and its miniaturization.
