This article overviews the design considerations and state-of-the-art of the ring voltage-controlled oscillator(VCO)-based phase-locked loops(PLLs)for clock generation in different applications.Partic-ularly,the objec...This article overviews the design considerations and state-of-the-art of the ring voltage-controlled oscillator(VCO)-based phase-locked loops(PLLs)for clock generation in different applications.Partic-ularly,the objective of the current work is to evaluate the required PLL performance among the fundamental metrics of power,jitter and area.An in-depth treatment of the mainstream PLL architectures and the associated design techniques enables them to be compared analyt-ically and benchmarked with respect to their figure-of-merit(FoM).The paper also summarizes the key concerns on the selection of dif-ferent circuit techniques to optimize the clock performance under dif-ferent scenarios.展开更多
提出一种适用于无源超高频射频识别(UHF RFID)标签芯片的时钟产生电路。电路使用N型金属-氧化物-半导体(NMOS)栅极电压取代了复杂的比较器电路作为比较电平,精简了电路结构,降低了电路功耗,减小了版图面积;使用二极管方式连接的NMOS管...提出一种适用于无源超高频射频识别(UHF RFID)标签芯片的时钟产生电路。电路使用N型金属-氧化物-半导体(NMOS)栅极电压取代了复杂的比较器电路作为比较电平,精简了电路结构,降低了电路功耗,减小了版图面积;使用二极管方式连接的NMOS管作温度及工艺补偿感应管,利用其栅压变化控制充放电电流,使其在不同工艺角下,当温度在较大范围内变化时,均能实现输出频率稳定。采用中芯国际0.18μm工艺进行仿真验证,结果表明:当电源电压为1 V,基准电流为130 n A时,电路功耗仅为447 n W;在工艺角由ss变化到ff的过程中,输出频率偏差不超过2.43%,;温度在-40~90℃范围变化时,输出频率偏差小于0.99%,适合无源射频识别标签芯片使用。展开更多
A 35-130 MHz/300-360 MHz phase-locked loop frequency synthesizer for △-∑ analog-to-digital con- verter （ADC） in 65 nm CMOS is presented. The frequency synthesizer can work in low phase-noise mode （300-360 MHz） o...A 35-130 MHz/300-360 MHz phase-locked loop frequency synthesizer for △-∑ analog-to-digital con- verter （ADC） in 65 nm CMOS is presented. The frequency synthesizer can work in low phase-noise mode （300-360 MHz） or in low-power mode （35-130 MHz） to satisfy the ADC＇s requirements. To switch between these two modes, a high frequency GHz LC VCO followed by a divided-by-four frequency divider and a low frequency ring VCO followed by a divided-by-two frequency divider are integrated on-chip. The measured results show that the fre- quency synthesizer achieves a phase-noise of-132 dBc/Hz at 1 MHz offset and an integrated RMS jitter of 1.12 ps with 1.74 mW power consumption from a 1.2 V power supply in low phase-noise mode. In low-power mode, the frequency synthesizer achieves a phase-noise of-112 dBc/Hz at 1 MHz offset and an integrated RMS jitter of 7.23 ps with 0.92 mW power consumption from a 1.2 V power supply.展开更多
基金supported by the National Natural Science Foundation of China under Grant 62004028,62090041the Science Foundation of Sichuan under Grant 2022NSFSC0927.
文摘This article overviews the design considerations and state-of-the-art of the ring voltage-controlled oscillator(VCO)-based phase-locked loops(PLLs)for clock generation in different applications.Partic-ularly,the objective of the current work is to evaluate the required PLL performance among the fundamental metrics of power,jitter and area.An in-depth treatment of the mainstream PLL architectures and the associated design techniques enables them to be compared analyt-ically and benchmarked with respect to their figure-of-merit(FoM).The paper also summarizes the key concerns on the selection of dif-ferent circuit techniques to optimize the clock performance under dif-ferent scenarios.
文摘提出一种适用于无源超高频射频识别(UHF RFID)标签芯片的时钟产生电路。电路使用N型金属-氧化物-半导体(NMOS)栅极电压取代了复杂的比较器电路作为比较电平,精简了电路结构,降低了电路功耗,减小了版图面积;使用二极管方式连接的NMOS管作温度及工艺补偿感应管,利用其栅压变化控制充放电电流,使其在不同工艺角下,当温度在较大范围内变化时,均能实现输出频率稳定。采用中芯国际0.18μm工艺进行仿真验证,结果表明:当电源电压为1 V,基准电流为130 n A时,电路功耗仅为447 n W;在工艺角由ss变化到ff的过程中,输出频率偏差不超过2.43%,;温度在-40~90℃范围变化时,输出频率偏差小于0.99%,适合无源射频识别标签芯片使用。
文摘A 35-130 MHz/300-360 MHz phase-locked loop frequency synthesizer for △-∑ analog-to-digital con- verter （ADC） in 65 nm CMOS is presented. The frequency synthesizer can work in low phase-noise mode （300-360 MHz） or in low-power mode （35-130 MHz） to satisfy the ADC＇s requirements. To switch between these two modes, a high frequency GHz LC VCO followed by a divided-by-four frequency divider and a low frequency ring VCO followed by a divided-by-two frequency divider are integrated on-chip. The measured results show that the fre- quency synthesizer achieves a phase-noise of-132 dBc/Hz at 1 MHz offset and an integrated RMS jitter of 1.12 ps with 1.74 mW power consumption from a 1.2 V power supply in low phase-noise mode. In low-power mode, the frequency synthesizer achieves a phase-noise of-112 dBc/Hz at 1 MHz offset and an integrated RMS jitter of 7.23 ps with 0.92 mW power consumption from a 1.2 V power supply.
