In this paper, the three-dimensional （3D） coupling effect is discussed for nanowire junctionless silicon-on-insulator （SOI） FinFETs. With fin width decreasing from 100 nm to 7 nm, the electric field induced by the...In this paper, the three-dimensional （3D） coupling effect is discussed for nanowire junctionless silicon-on-insulator （SOI） FinFETs. With fin width decreasing from 100 nm to 7 nm, the electric field induced by the lateral gates increases and therefore the influence of back gate on the threshold voltage weakens. For a narrow and tall fin, the lateral gates mainly control the channel and therefore the effect of back gate decreases. A simple two-dimensional （2D） potential model is proposed for the subthreshold region of junctionless SO1 FinFET. TCAD simulations validate our model. It can be used to extract the threshold voltage and doping concentration. In addition, the tuning of back gate on the threshold voltage can be predicted.展开更多
The hot-carrier effect charactenstic in a deep submicron partially depleted SOI NMOSFET is investigated. Obvious hot-carrier degradation is observed under off-state stress.The hot-carrier damage is supposed to be indu...The hot-carrier effect charactenstic in a deep submicron partially depleted SOI NMOSFET is investigated. Obvious hot-carrier degradation is observed under off-state stress.The hot-carrier damage is supposed to be induced by the parasitic bipolar effects of a float SOI device.The back channel also suffers degradation from the hot carrier in the drain depletion region as well as the front channel.At low gate voltage,there is a hump in the sub-threshold curve of the back gate transistor,and it does not shift in the same way as the main transistor under stress.While under the same condition,there is a more severe hot-carrier effect with a shorter channel transistor. The reasons for those phenomena are discussed in detail.展开更多
The stability of a graphene field effect transistor（GFET） is important to its performance optimization, and study of hysteresis behavior can propose useful suggestions for GFET fabrication and optimization.In this w...The stability of a graphene field effect transistor（GFET） is important to its performance optimization, and study of hysteresis behavior can propose useful suggestions for GFET fabrication and optimization.In this work,a back-gate GFET has been fabricated and characterized,which is compatible with the CMOS process.The stability of a GFET in air has been studied and it is found that a GFET＇s electrical performance dramatically changes when exposed to air.The hysteresis characteristic of a GFET depending on time has been observed and analyzed systematically.Hysteresis behavior is reversed at room temperature with the Dirac point positive shifted when the GFET is exposed to air after annealing.展开更多
A non-depletion floating layer silicon-on-insulator （NFL SOI） lateral double-diffused metal–oxide–semiconductor （LDMOS） is proposed and the NFL-assisted modulated field （NFLAMF） principle is investigated in th...A non-depletion floating layer silicon-on-insulator （NFL SOI） lateral double-diffused metal–oxide–semiconductor （LDMOS） is proposed and the NFL-assisted modulated field （NFLAMF） principle is investigated in this paper. Based on this principle, the floating layer can pin the potential for modulating bulk field. In particular, the accumulated high concentration of holes at the bottom of the NFL can efficiently shield the electric field of the SOI layer and enhance the dielectric field in the buried oxide layer （BOX）. At variation of back-gate bias, the shielding charges of NFL can also eliminate back-gate effects. The simulated results indicate that the breakdown voltage （BV） is increased from 315 V to 558 V compared to the conventional reduced surface field （RESURF） SOI （CSOI） LDMOS, yielding a 77% improvement. Furthermore, due to the field shielding effect of the NFL, the device can maintain the same breakdown voltage of 558 V with a thinner BOX to resolve the thermal problem in an SOI device.展开更多
A uniform doping ultra-thin silicon-on-insulator（SOI） lateral-double-diffused metal-oxide-semiconductor（LDMOS）with low specific on-resistance（R_on,sp） and high breakdown voltage（BV） is proposed and its mechani...A uniform doping ultra-thin silicon-on-insulator（SOI） lateral-double-diffused metal-oxide-semiconductor（LDMOS）with low specific on-resistance（R_on,sp） and high breakdown voltage（BV） is proposed and its mechanism is investigated.The proposed LDMOS features an accumulation-mode extended gate（AG） and back-side etching（BE）. The extended gate consists of a P– region and two diodes in series. In the on-state with VGD〉 0, an electron accumulation layer is formed along the drift region surface under the AG. It provides an ultra-low resistance current path along the whole drift region surface and thus the novel device obtains a low temperature distribution. The R_on,sp is nearly independent of the doping concentration of the drift region. In the off-state, the AG not only modulates the surface electric field distribution and improves the BV, but also brings in a charge compensation effect to further reduce the R_on,sp. Moreover, the BE avoids vertical premature breakdown to obtain high BV and allows a uniform doping in the drift region, which avoids the variable lateral doping（VLD） and the ＂hot-spot＂ caused by the VLD. Compared with the VLD SOI LDMOS, the proposed device simultaneously reduces the R_on,sp by 70.2% and increases the BV from 776 V to 818 V.展开更多
Deep ultraviolet(DUV)phototransistors are key integral of optoelectronics bearing a wide spectrum of applications in flame sensor,military detector,oil spill detection,biological sensor,and artificial intelligence fie...Deep ultraviolet(DUV)phototransistors are key integral of optoelectronics bearing a wide spectrum of applications in flame sensor,military detector,oil spill detection,biological sensor,and artificial intelligence fields.In order to further improve the responsivity of UV photodetectors based onβ-Ga_(2)O_(3),in present work,high-performanceβ-Ga_(2)O_(3) phototransistors with local back-gate structure were experimentally demonstrated.The phototransistor shows excellent DUV photoelectrical performance with a high responsivity of 1.01×107 A/W,a high external quantum efficiency of 5.02×109%,a sensitive detectivity of 2.98×1015 Jones,and a fast rise time of 0.2 s under 250 nm illumination.Besides,first-principles calculations reveal the decent stability ofβGa_(2)O_(3) nanosheet against oxidation and humidity without significant performance degradations.Additionally,the hexagonal boron nitride(h-BN)/β-Ga_(2)O_(3) phototransistor can behave as a photonic synapse with ultralow power consumption of~9.6 fJ per spike,which shows its potential for neuromorphic computing tasks such as facial recognition.Thisβ-Ga_(2)O_(3) phototransistor will provide a perspective for the next generation optoelectrical systems.展开更多
The fabrication and photoelectrical characteristics of suspended ZnO nanowire （NW） field-effect transistors （FETs） are presented. Single-crystal ZnO NWs are synthesized by a hydrothermal method. The fabricated FET...The fabrication and photoelectrical characteristics of suspended ZnO nanowire （NW） field-effect transistors （FETs） are presented. Single-crystal ZnO NWs are synthesized by a hydrothermal method. The fabricated FETs exhibit excellent performance. When Vds=2.5 V, the peak transconductance of the FETs is 0.396 μS, the average electron mobility is 50.17 cm2/（V·s）, the resistivity is 0.96 × 102 Ω·cm at Vgs = 0 V, and the current on/off ratio （Ion/Ioff） is approximately 105. ZnO NW-FET devices exposed to ultraviolet radiation （2.5 μW/cm2） exhibit punch-through and threshold voltage （Vth） shift （from-0.6 V to ＋0.7 V） and a decrease by almost half of the source-drain current （Ids, from 560 nA to 320 nA） due to drain-induced barrier lowering. Continued work is underway to reveal the intrinsic properties of suspended ZnO nanowires and to explore their device applications.展开更多
This paper reports that a novel type of suspended ZnO nanowire field-effect transistors （FETs） were successfully fabricated using a photolithography process, and their electrical properties were characterized by I-V...This paper reports that a novel type of suspended ZnO nanowire field-effect transistors （FETs） were successfully fabricated using a photolithography process, and their electrical properties were characterized by I-V measurements. Single-crystalline ZnO nanowires were synthesized by a hydrothermal method, they were used as a suspended ZnO nanowire channel of back-gate field-effect transistors （FET）. The fabricated suspended nanowire FETs showed a pchannel depletion mode, exhibited high on-off current ratio of -10^5. When VDS = 2.5V, the peak transconductances of the suspended FETs were 0.396 μS, the oxide capacitance was found to be 1.547 fF, the pinch-off voltage VTH was about 0.6 V, the electron mobility was on average 50.17cm2/Vs. The resistivity of the ZnO nanowire channel was estimated to be 0.96 × 10^2 Ω cm at VGS = 0 V. These characteristics revealed that the suspended nanowire FET fabricated by the photolithography process had excellent performance. Better contacts between the ZnO nanowire and metal electrodes could be improved through annealing and metal deposition using a focused ion beam.展开更多
The performance of a LOCOS-isolated SOI MOSFET heavily depends on its back-gate characteristic, which can be affected by back-gate stress.A large voltage stress was applied to the back gate of SOI devices for at least...The performance of a LOCOS-isolated SOI MOSFET heavily depends on its back-gate characteristic, which can be affected by back-gate stress.A large voltage stress was applied to the back gate of SOI devices for at least 30 s at room temperature,which could effectively modify the back-gate threshold voltage of these devices. This modification is stable and time invariant.In order to improve the back-gate threshold voltage,positive substrate bias was applied to NMOS devices and negative substrate bias was applied to PMOS devices.These results suggest that there is a leakage path between source and drain along the silicon island edge,and the application of large backgate bias with the source,drain and gate grounded can strongly affect this leakage path.So we draw the conclusion that the back-gate threshold voltage,which is directly related to the leakage current,can be influenced by back-gate stress.展开更多
An LDMOS with nearly rectangular-shape safe operation area （SOA） and low specific on-resistance is proposed. By utilizing a split gate, an electron accumulation layer is formed near the surface of the n-drift region...An LDMOS with nearly rectangular-shape safe operation area （SOA） and low specific on-resistance is proposed. By utilizing a split gate, an electron accumulation layer is formed near the surface of the n-drift region to improve current conduction capability during on-state operation. As a result, the specific on-resistance can be low- ered down to 74.7 m^2.cm2 for a 600 V device from simulation. Furthermore, under high-voltage and high-current conditions, electrons and holes flow as majority carriers in the n-drift region and p-type split gate, respectively. Due to charge compensation occurring between holes and electrons, the local electric field is reduced and impact ion- ization is weakened in the proposed device. Therefore, a higher on-state breakdown voltage at large V6s is obtained and snap-back is suppressed as well.展开更多
We show the fabrication of flexible graphene devices with an embedded backgate. The resistance of these devices can be tuned by changing the strain through the bending of the substrate. These devices can be useful for...We show the fabrication of flexible graphene devices with an embedded backgate. The resistance of these devices can be tuned by changing the strain through the bending of the substrate. These devices can be useful for applications requiring a flexible graphene-based field effect transistor in where the graphene channel is not covered (such as biological or chemical sensors and photo-detectors).展开更多
This paper discusses the breakdown mechanism and proposes a new simulation and test method of breakdown voltage （BV） for an ultra-high-voltage （UHV） high-side thin layer silicon-on-insulator （SOI） p-channel low-...This paper discusses the breakdown mechanism and proposes a new simulation and test method of breakdown voltage （BV） for an ultra-high-voltage （UHV） high-side thin layer silicon-on-insulator （SOI） p-channel low-density metal- oxide semiconductor （LDMOS）. Compared with the conventional simulation method, the new one is more accordant with the actual conditions of a device that can be used in the high voltage circuit. The BV of the SOI p-channel LDMOS can be properly represented and the effect of reduced bulk field can be revealed by employing the new simulation method. Simulation results show that the off-state （on-state） BV of the SOI p-channel LDMOS can reach 741 （620） V in the 3μm-thick buried oxide layer, 50μm-length drift region, and at -400 V back-gate voltage, enabling the device to be used in a 400 V UHV integrated circuit.展开更多
Planarization used in a gate-last CMOS device was successfully developed by particular technologies of SOG two-step plasma etch-back plus one special etch-back step for SOG/SiO_2 interface trimming.The within-the-wafe...Planarization used in a gate-last CMOS device was successfully developed by particular technologies of SOG two-step plasma etch-back plus one special etch-back step for SOG/SiO_2 interface trimming.The within-the-wafer ILD thickness non-uniformity can reach 4.19%with a wafer edge exclusion of 5 mm.SEM results indicated that there was little＂dish effect＂on the 0.4μm gate-stack structure and finally achieved a good planarization profile on the whole substrate.The technology provided a CMP-less process basis for sub-100 nm high-k/metal gate-last CMOS integration.展开更多
The DC and RF performance of 30 nm gate length enhancement mode （E-mode） InAlN/AIN/GaN high electron mobility transistor （HEMT） on SiC substrate with heavily doped source and drain region have been inves- tigated ...The DC and RF performance of 30 nm gate length enhancement mode （E-mode） InAlN/AIN/GaN high electron mobility transistor （HEMT） on SiC substrate with heavily doped source and drain region have been inves- tigated using the Synopsys TCAD tool. The proposed device has the features of a recessed T-gate structure, lnGaN back barrier and Al2O3 passivated device surface. The proposed HEMT exhibits a maximum drain current density of 2.1 A/mm, transconductance gm of 1050 mS/mm, current gain cut-off frequency f of 350 GHz and power gain cut-off frequency fmax of 340 GHz. At room temperature the measured carrier mobility （μ）, sheet charge carrier density （ns） and breakdown voltage are 1580 cm2/（V.s）, 1.9× 1013 cm-2, and 10.7 V respectively. The superla- tives of the proposed HEMTs are bewitching competitor or future sub-millimeter wave high power RF VLSI circuit applications.展开更多
Ultra-thin-body （UTB） In0.53Ga0.47As-on-insulator （In0.53Ga0.47As-OI） structures with thicknesses of 8 and 15nm are realized by transferring epitaxially grown In0.53Ga0.47As layers to silicon substrates with 15-nm...Ultra-thin-body （UTB） In0.53Ga0.47As-on-insulator （In0.53Ga0.47As-OI） structures with thicknesses of 8 and 15nm are realized by transferring epitaxially grown In0.53Ga0.47As layers to silicon substrates with 15-nmthick A12 03 as a buried oxide by using the direct wafer bonding method. Back gate n-channel metal-oxidesemiconductor field-effect transistors （nMOSFETs） are fabricated by using these In0.53Ga0.47As-OI structures with excellent electrical characteristics. Positive bias temperature instability （PBTI） and hot carrier injection （HCI） characterizations are performed for the In0.53Ga0.47As-OI nMOSFETs. It is confirmed that the In0.53Ga0.47 As-OI nMOSFETs with a thinner body thickness suffer from more severe degradations under both PBTI and HCr stresses. Moreover, the different evolutions of the threshold voltage and the saturation current of the UTB In0.53Ga0.47As-OI nMOSFETs may be due to the slow border traps.展开更多
An optimized commutation method based on backpropagation(BP)neural network is proposed to resolve the low stability and high-power consumption caused by inaccurate commutation point prediction in conventional commutat...An optimized commutation method based on backpropagation(BP)neural network is proposed to resolve the low stability and high-power consumption caused by inaccurate commutation point prediction in conventional commutation strategy during acceleration and deceleration.This article also builds a complete brushless DC motor drive system based on the GD32F103 micro control unit(MCU),with an Artix-7 XC7A35T field programmable gate array(FPGA)to meet the performance requirements of neural network calculation for real-time motor commutation control.Experimental results show that the proposed optimization strategy can effectively improve the system stability during system acceleration and deceleration,and reduce the current spikes generated during speed chan-ges.The system power consumption is reduced by about 11.7%on average.展开更多
基金supported by the Research Program of the National University of Defense Technology(Grant No.JC 13-06-04)
文摘In this paper, the three-dimensional （3D） coupling effect is discussed for nanowire junctionless silicon-on-insulator （SOI） FinFETs. With fin width decreasing from 100 nm to 7 nm, the electric field induced by the lateral gates increases and therefore the influence of back gate on the threshold voltage weakens. For a narrow and tall fin, the lateral gates mainly control the channel and therefore the effect of back gate decreases. A simple two-dimensional （2D） potential model is proposed for the subthreshold region of junctionless SO1 FinFET. TCAD simulations validate our model. It can be used to extract the threshold voltage and doping concentration. In addition, the tuning of back gate on the threshold voltage can be predicted.
文摘The hot-carrier effect charactenstic in a deep submicron partially depleted SOI NMOSFET is investigated. Obvious hot-carrier degradation is observed under off-state stress.The hot-carrier damage is supposed to be induced by the parasitic bipolar effects of a float SOI device.The back channel also suffers degradation from the hot carrier in the drain depletion region as well as the front channel.At low gate voltage,there is a hump in the sub-threshold curve of the back gate transistor,and it does not shift in the same way as the main transistor under stress.While under the same condition,there is a more severe hot-carrier effect with a shorter channel transistor. The reasons for those phenomena are discussed in detail.
基金supported by the National Sciences and Technology Major Project 02
文摘The stability of a graphene field effect transistor（GFET） is important to its performance optimization, and study of hysteresis behavior can propose useful suggestions for GFET fabrication and optimization.In this work,a back-gate GFET has been fabricated and characterized,which is compatible with the CMOS process.The stability of a GFET in air has been studied and it is found that a GFET＇s electrical performance dramatically changes when exposed to air.The hysteresis characteristic of a GFET depending on time has been observed and analyzed systematically.Hysteresis behavior is reversed at room temperature with the Dirac point positive shifted when the GFET is exposed to air after annealing.
文摘A non-depletion floating layer silicon-on-insulator （NFL SOI） lateral double-diffused metal–oxide–semiconductor （LDMOS） is proposed and the NFL-assisted modulated field （NFLAMF） principle is investigated in this paper. Based on this principle, the floating layer can pin the potential for modulating bulk field. In particular, the accumulated high concentration of holes at the bottom of the NFL can efficiently shield the electric field of the SOI layer and enhance the dielectric field in the buried oxide layer （BOX）. At variation of back-gate bias, the shielding charges of NFL can also eliminate back-gate effects. The simulated results indicate that the breakdown voltage （BV） is increased from 315 V to 558 V compared to the conventional reduced surface field （RESURF） SOI （CSOI） LDMOS, yielding a 77% improvement. Furthermore, due to the field shielding effect of the NFL, the device can maintain the same breakdown voltage of 558 V with a thinner BOX to resolve the thermal problem in an SOI device.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61176069 and 61376079)
文摘A uniform doping ultra-thin silicon-on-insulator（SOI） lateral-double-diffused metal-oxide-semiconductor（LDMOS）with low specific on-resistance（R_on,sp） and high breakdown voltage（BV） is proposed and its mechanism is investigated.The proposed LDMOS features an accumulation-mode extended gate（AG） and back-side etching（BE）. The extended gate consists of a P– region and two diodes in series. In the on-state with VGD〉 0, an electron accumulation layer is formed along the drift region surface under the AG. It provides an ultra-low resistance current path along the whole drift region surface and thus the novel device obtains a low temperature distribution. The R_on,sp is nearly independent of the doping concentration of the drift region. In the off-state, the AG not only modulates the surface electric field distribution and improves the BV, but also brings in a charge compensation effect to further reduce the R_on,sp. Moreover, the BE avoids vertical premature breakdown to obtain high BV and allows a uniform doping in the drift region, which avoids the variable lateral doping（VLD） and the ＂hot-spot＂ caused by the VLD. Compared with the VLD SOI LDMOS, the proposed device simultaneously reduces the R_on,sp by 70.2% and increases the BV from 776 V to 818 V.
基金supported by the National Natural Science Foundation of China(Nos.62027818,61874034,51861135105,and 51972319)International Science and Technology Cooperation Program of Shanghai Science and Technology Innovation Action Plan(No.21520713300)Science and Technology Commission of Shanghai Municipality(No.19520744400).
文摘Deep ultraviolet(DUV)phototransistors are key integral of optoelectronics bearing a wide spectrum of applications in flame sensor,military detector,oil spill detection,biological sensor,and artificial intelligence fields.In order to further improve the responsivity of UV photodetectors based onβ-Ga_(2)O_(3),in present work,high-performanceβ-Ga_(2)O_(3) phototransistors with local back-gate structure were experimentally demonstrated.The phototransistor shows excellent DUV photoelectrical performance with a high responsivity of 1.01×107 A/W,a high external quantum efficiency of 5.02×109%,a sensitive detectivity of 2.98×1015 Jones,and a fast rise time of 0.2 s under 250 nm illumination.Besides,first-principles calculations reveal the decent stability ofβGa_(2)O_(3) nanosheet against oxidation and humidity without significant performance degradations.Additionally,the hexagonal boron nitride(h-BN)/β-Ga_(2)O_(3) phototransistor can behave as a photonic synapse with ultralow power consumption of~9.6 fJ per spike,which shows its potential for neuromorphic computing tasks such as facial recognition.Thisβ-Ga_(2)O_(3) phototransistor will provide a perspective for the next generation optoelectrical systems.
基金supported by the State Key Development Program for Basic Research of China(No.2002CB311901)the Director Fund of the Institute of Microelectronic of the Chinese Academy of Sciences (No.O8SB034002)the Pre-Research Fund of Weap on Equipment (No.6150105040)
文摘The fabrication and photoelectrical characteristics of suspended ZnO nanowire （NW） field-effect transistors （FETs） are presented. Single-crystal ZnO NWs are synthesized by a hydrothermal method. The fabricated FETs exhibit excellent performance. When Vds=2.5 V, the peak transconductance of the FETs is 0.396 μS, the average electron mobility is 50.17 cm2/（V·s）, the resistivity is 0.96 × 102 Ω·cm at Vgs = 0 V, and the current on/off ratio （Ion/Ioff） is approximately 105. ZnO NW-FET devices exposed to ultraviolet radiation （2.5 μW/cm2） exhibit punch-through and threshold voltage （Vth） shift （from-0.6 V to ＋0.7 V） and a decrease by almost half of the source-drain current （Ids, from 560 nA to 320 nA） due to drain-induced barrier lowering. Continued work is underway to reveal the intrinsic properties of suspended ZnO nanowires and to explore their device applications.
文摘This paper reports that a novel type of suspended ZnO nanowire field-effect transistors （FETs） were successfully fabricated using a photolithography process, and their electrical properties were characterized by I-V measurements. Single-crystalline ZnO nanowires were synthesized by a hydrothermal method, they were used as a suspended ZnO nanowire channel of back-gate field-effect transistors （FET）. The fabricated suspended nanowire FETs showed a pchannel depletion mode, exhibited high on-off current ratio of -10^5. When VDS = 2.5V, the peak transconductances of the suspended FETs were 0.396 μS, the oxide capacitance was found to be 1.547 fF, the pinch-off voltage VTH was about 0.6 V, the electron mobility was on average 50.17cm2/Vs. The resistivity of the ZnO nanowire channel was estimated to be 0.96 × 10^2 Ω cm at VGS = 0 V. These characteristics revealed that the suspended nanowire FET fabricated by the photolithography process had excellent performance. Better contacts between the ZnO nanowire and metal electrodes could be improved through annealing and metal deposition using a focused ion beam.
基金supported by the National Natural Science Foundation of China(No.60927006)the Major Projects of National Science and Technology
文摘The performance of a LOCOS-isolated SOI MOSFET heavily depends on its back-gate characteristic, which can be affected by back-gate stress.A large voltage stress was applied to the back gate of SOI devices for at least 30 s at room temperature,which could effectively modify the back-gate threshold voltage of these devices. This modification is stable and time invariant.In order to improve the back-gate threshold voltage,positive substrate bias was applied to NMOS devices and negative substrate bias was applied to PMOS devices.These results suggest that there is a leakage path between source and drain along the silicon island edge,and the application of large backgate bias with the source,drain and gate grounded can strongly affect this leakage path.So we draw the conclusion that the back-gate threshold voltage,which is directly related to the leakage current,can be influenced by back-gate stress.
基金Project supported in part by the National Natural Science Foundation of China(No.51237001)
文摘An LDMOS with nearly rectangular-shape safe operation area （SOA） and low specific on-resistance is proposed. By utilizing a split gate, an electron accumulation layer is formed near the surface of the n-drift region to improve current conduction capability during on-state operation. As a result, the specific on-resistance can be low- ered down to 74.7 m^2.cm2 for a 600 V device from simulation. Furthermore, under high-voltage and high-current conditions, electrons and holes flow as majority carriers in the n-drift region and p-type split gate, respectively. Due to charge compensation occurring between holes and electrons, the local electric field is reduced and impact ion- ization is weakened in the proposed device. Therefore, a higher on-state breakdown voltage at large V6s is obtained and snap-back is suppressed as well.
文摘We show the fabrication of flexible graphene devices with an embedded backgate. The resistance of these devices can be tuned by changing the strain through the bending of the substrate. These devices can be useful for applications requiring a flexible graphene-based field effect transistor in where the graphene channel is not covered (such as biological or chemical sensors and photo-detectors).
基金Project supported by the National Natural Science Foundation of China (Grant No. 60906038)
文摘This paper discusses the breakdown mechanism and proposes a new simulation and test method of breakdown voltage （BV） for an ultra-high-voltage （UHV） high-side thin layer silicon-on-insulator （SOI） p-channel low-density metal- oxide semiconductor （LDMOS）. Compared with the conventional simulation method, the new one is more accordant with the actual conditions of a device that can be used in the high voltage circuit. The BV of the SOI p-channel LDMOS can be properly represented and the effect of reduced bulk field can be revealed by employing the new simulation method. Simulation results show that the off-state （on-state） BV of the SOI p-channel LDMOS can reach 741 （620） V in the 3μm-thick buried oxide layer, 50μm-length drift region, and at -400 V back-gate voltage, enabling the device to be used in a 400 V UHV integrated circuit.
基金Project supported by the Chinese National Science and Technology Major Project(No.2009ZX02035)the Special Funds for Major State Basic Research Projects,China(No.2006CB302704)the Opening Project of Key Laboratory of Microelectronics Devices of Integrated Technology(IMECAS)
文摘Planarization used in a gate-last CMOS device was successfully developed by particular technologies of SOG two-step plasma etch-back plus one special etch-back step for SOG/SiO_2 interface trimming.The within-the-wafer ILD thickness non-uniformity can reach 4.19%with a wafer edge exclusion of 5 mm.SEM results indicated that there was little＂dish effect＂on the 0.4μm gate-stack structure and finally achieved a good planarization profile on the whole substrate.The technology provided a CMP-less process basis for sub-100 nm high-k/metal gate-last CMOS integration.
文摘The DC and RF performance of 30 nm gate length enhancement mode （E-mode） InAlN/AIN/GaN high electron mobility transistor （HEMT） on SiC substrate with heavily doped source and drain region have been inves- tigated using the Synopsys TCAD tool. The proposed device has the features of a recessed T-gate structure, lnGaN back barrier and Al2O3 passivated device surface. The proposed HEMT exhibits a maximum drain current density of 2.1 A/mm, transconductance gm of 1050 mS/mm, current gain cut-off frequency f of 350 GHz and power gain cut-off frequency fmax of 340 GHz. At room temperature the measured carrier mobility （μ）, sheet charge carrier density （ns） and breakdown voltage are 1580 cm2/（V.s）, 1.9× 1013 cm-2, and 10.7 V respectively. The superla- tives of the proposed HEMTs are bewitching competitor or future sub-millimeter wave high power RF VLSI circuit applications.
基金Supported by the National Program on Key Basic Research Project of China under Grant No 2011CBA00607the National Natural Science Foundation of China under Grant Nos 61106089 and 61376097the Zhejiang Provincial Natural Science Foundation of China under Grant No LR14F040001
文摘Ultra-thin-body （UTB） In0.53Ga0.47As-on-insulator （In0.53Ga0.47As-OI） structures with thicknesses of 8 and 15nm are realized by transferring epitaxially grown In0.53Ga0.47As layers to silicon substrates with 15-nmthick A12 03 as a buried oxide by using the direct wafer bonding method. Back gate n-channel metal-oxidesemiconductor field-effect transistors （nMOSFETs） are fabricated by using these In0.53Ga0.47As-OI structures with excellent electrical characteristics. Positive bias temperature instability （PBTI） and hot carrier injection （HCI） characterizations are performed for the In0.53Ga0.47As-OI nMOSFETs. It is confirmed that the In0.53Ga0.47 As-OI nMOSFETs with a thinner body thickness suffer from more severe degradations under both PBTI and HCr stresses. Moreover, the different evolutions of the threshold voltage and the saturation current of the UTB In0.53Ga0.47As-OI nMOSFETs may be due to the slow border traps.
基金the National Key Research and Development Program(No.2017YFB0406204,2016YFC0105604)Beijing Science and Technology Projects(No.Z181100003818002)Science and Technology Service Network Initiative(No.FJ-STS-QYZX-099,KFJ-STS-ZDTP-069).
文摘An optimized commutation method based on backpropagation(BP)neural network is proposed to resolve the low stability and high-power consumption caused by inaccurate commutation point prediction in conventional commutation strategy during acceleration and deceleration.This article also builds a complete brushless DC motor drive system based on the GD32F103 micro control unit(MCU),with an Artix-7 XC7A35T field programmable gate array(FPGA)to meet the performance requirements of neural network calculation for real-time motor commutation control.Experimental results show that the proposed optimization strategy can effectively improve the system stability during system acceleration and deceleration,and reduce the current spikes generated during speed chan-ges.The system power consumption is reduced by about 11.7%on average.
