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A uniform doping ultra-thin SOI LDMOS with accumulation-mode extended gate and back-side etching technology 被引量:1

A uniform doping ultra-thin SOI LDMOS with accumulation-mode extended gate and back-side etching technology
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摘要 A uniform doping ultra-thin silicon-on-insulator(SOI) lateral-double-diffused metal-oxide-semiconductor(LDMOS)with low specific on-resistance(R_on,sp) and high breakdown voltage(BV) is proposed and its mechanism is investigated.The proposed LDMOS features an accumulation-mode extended gate(AG) and back-side etching(BE). The extended gate consists of a P– region and two diodes in series. In the on-state with VGD〉 0, an electron accumulation layer is formed along the drift region surface under the AG. It provides an ultra-low resistance current path along the whole drift region surface and thus the novel device obtains a low temperature distribution. The R_on,sp is nearly independent of the doping concentration of the drift region. In the off-state, the AG not only modulates the surface electric field distribution and improves the BV, but also brings in a charge compensation effect to further reduce the R_on,sp. Moreover, the BE avoids vertical premature breakdown to obtain high BV and allows a uniform doping in the drift region, which avoids the variable lateral doping(VLD) and the "hot-spot" caused by the VLD. Compared with the VLD SOI LDMOS, the proposed device simultaneously reduces the R_on,sp by 70.2% and increases the BV from 776 V to 818 V. A uniform doping ultra-thin silicon-on-insulator(SOI) lateral-double-diffused metal-oxide-semiconductor(LDMOS)with low specific on-resistance(R_on,sp) and high breakdown voltage(BV) is proposed and its mechanism is investigated.The proposed LDMOS features an accumulation-mode extended gate(AG) and back-side etching(BE). The extended gate consists of a P– region and two diodes in series. In the on-state with VGD〉 0, an electron accumulation layer is formed along the drift region surface under the AG. It provides an ultra-low resistance current path along the whole drift region surface and thus the novel device obtains a low temperature distribution. The R_on,sp is nearly independent of the doping concentration of the drift region. In the off-state, the AG not only modulates the surface electric field distribution and improves the BV, but also brings in a charge compensation effect to further reduce the R_on,sp. Moreover, the BE avoids vertical premature breakdown to obtain high BV and allows a uniform doping in the drift region, which avoids the variable lateral doping(VLD) and the "hot-spot" caused by the VLD. Compared with the VLD SOI LDMOS, the proposed device simultaneously reduces the R_on,sp by 70.2% and increases the BV from 776 V to 818 V.
出处 《Chinese Physics B》 SCIE EI CAS CSCD 2016年第2期436-440,共5页 中国物理B(英文版)
基金 Project supported by the National Natural Science Foundation of China(Grant Nos.61176069 and 61376079)
关键词 LDMOS accumulation gate back-side etching breakdown voltage specific on-resistance LDMOS, accumulation gate, back-side etching, breakdown voltage, specific on-resistance
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  • 1Ludikhuize A W 2001 Proceedings of the 31st Eurapean, 1EEE Solid- State Device Research Col!ference, September I 1-13, 2001, p. 35. 被引量:1
  • 2lqbal M M, Udrea F and Napoli E 2009 IEEE Proceedings of the 21st International Symposium on Power Semiconductor Devices and ICs, June 14-18, 2009, Barcelona, Spain, p. 247. 被引量:1
  • 3Ming Q, Li Y F, Zhou X, Li Z J and Zhang B 2014 IEEE Electron Dev Lett. 35 774. 被引量:1
  • 4Chen X B U S Patent 5216275 [1993-06-01] Chen Y, Liang Y C, Samudra G S, Xin Y, Buddharaju K D and H H Feng 2008 IEEE Trans. Electron Dev 55 211. 被引量:1
  • 5Luo X, Wei J, Shi X, Zhou K, Tian R, Zhang B and Li Z 2014 IEEE Trans. Electron Dev. 61 4304. 被引量:1
  • 6Merchant S, Arnold E, Baumgart H, Mukherjee S, Pein H and Pinker R IOql Ib?t? Prot:aedins of the 3rd International Symposium on Power Semiconductor Devices and ICs, April 22-24, 1991, Maryland, USA, p. 31. 被引量:1
  • 7Luo X R, Wei J, Shi X L, Zhou K, Tian R C, Zhang B and Li Z J 2014 IEEE Trans. Electron. Dev 61 4304. 被引量:1
  • 8Luo X R, Wei J, Shi X L, Zhou K, Tian R C, Zhang B and Li Z J 2014 IEEE Trans. Electron. Dev. 61 4304. 被引量:1
  • 9Udrea F, Trajkovic T, Lee C, Garner D, Yuan X, Joyce J, Udugampola N, Bonnet G, Coulson D, Jacques R, Izmajlowicz M, van der Duijn Schouten N, Ansari Z, Moyse P and Amaratunga G A J 2005 1EEE Proceedings of the 17th International Symposiunl on Power Semicon- ductor Devices and lCs, Santa Barbara, USA, p. 267. 被引量:1
  • 10Leung Y K, Amit K E Kenneth E G, James D P and Wong S S 1997 IEEE Electron Dev. Lett. 18 414. 被引量:1

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