In mmWave massive multiple-input multiple-output(MIMO)communication systems,the extension of low-complexity narrowband precoding schemes to be operated on wideband systems under frequency-selective channels remains an...In mmWave massive multiple-input multiple-output(MIMO)communication systems,the extension of low-complexity narrowband precoding schemes to be operated on wideband systems under frequency-selective channels remains an important challenge at the current time.This paper investigates a low complexity wideband hybrid precoding scheme for mmWave massive MIMO multicarrier systems under a single-user,fully-connected hybrid architecture.We show that the radio frequency(RF)precoding/combining vectors can be directly derived from the eigenvectors of the optimal fully-digital covariance matrix over all subcarriers in order to maximize the sum rate of spectral efficiency.We also suggest a new method that iteratively reduces the residual error between the covariance matrix and the sum of products of precoding matrices over all the subcarriers to improve the performance in the case where the number of RF chains is higher than the number of streams.The results of the simulation show that the proposed schemes’complexity is low compared to the present methods,and their performance can almost reach the upper bound achieved by the optimal full-baseband design.展开更多
Large number of antennas and higher bandwidth usage in massive multiple-input-multipleoutput(MIMO)systems create immense burden on receiver in terms of higher power consumption.The power consumption at the receiver ra...Large number of antennas and higher bandwidth usage in massive multiple-input-multipleoutput(MIMO)systems create immense burden on receiver in terms of higher power consumption.The power consumption at the receiver radio frequency(RF)circuits can be significantly reduced by the application of analog-to-digital converter(ADC)of low resolution.In this paper we investigate bandwidth efficiency(BE)of massive MIMO with perfect channel state information(CSI)by applying low resolution ADCs with Rician fadings.We start our analysis by deriving the additive quantization noise model,which helps to understand the effects of ADC resolution on BE by keeping the power constraint at the receiver in radar.We also investigate deeply the effects of using higher bit rates and the number of BS antennas on bandwidth efficiency(BE)of the system.We emphasize that good bandwidth efficiency can be achieved by even using low resolution ADC by using regularized zero-forcing(RZF)combining algorithm.We also provide a generic analysis of energy efficiency(EE)with different options of bits by calculating the energy efficiencies(EE)using the achievable rates.We emphasize that satisfactory BE can be achieved by even using low-resolution ADC/DAC in massive MIMO.展开更多
An analog/digital reconfigurable automatic gain control （AGC） circuit with a novel DC offset cancel- lation circuit for a direct-conversion receiver is presented. The AGC is analog/digital reconfigurable in order to...An analog/digital reconfigurable automatic gain control （AGC） circuit with a novel DC offset cancel- lation circuit for a direct-conversion receiver is presented. The AGC is analog/digital reconfigurable in order to be compatible with different baseband chips. What＇s more, a novel DC offset cancellation （DCOC） circuit with an HPCF （high pass cutoff frequency） less than 10 kHz is proposed. The AGC is fabricated by a 0.18μm CMOS process. Under analog control mode, the AGC achieves a 70 dB dynamic range with a 3 dB-bandwidth larger than 60 MHz. Under digital control mode, through a 5-bit digital control word, the AGC shows a 64 dB gain control range by 2 dB each step with a gain error of less than 0.3 dB. The DC offset cancellation circuits can suppress the output DC offset voltage to be less than 1.5 mV, while the offset voltage of 40 mV is introduced into the input. The overall power consumption is less than 3.5 mA, and the die area is 800 ×300μm2.展开更多
A continuously or/and discontinuously tunable LiNbO3 Optical Parametric Oscillator (OPO) with the spectral range of 1.42 - 4.24 um and shifting of 0…12 nm is created and investigated. The OPO resonator ring circuit p...A continuously or/and discontinuously tunable LiNbO3 Optical Parametric Oscillator (OPO) with the spectral range of 1.42 - 4.24 um and shifting of 0…12 nm is created and investigated. The OPO resonator ring circuit provides for the radiation energy output value of up to 50 mJ. Radiation bandwidth narrowing of up to 0.7 cm–1 by introducing of the Fabry-Perot etalon into the OPO resonator has been obtained.展开更多
We first clarify timing issues of non-uniform sampling intervals regarding a 5 GS/s fast pulse sampling module with DRS4. A calibration strategy is proposed, and as a result, the waveform timing performance is improve...We first clarify timing issues of non-uniform sampling intervals regarding a 5 GS/s fast pulse sampling module with DRS4. A calibration strategy is proposed, and as a result, the waveform timing performance is improved to below 10 ps RMS. We then further evaluate waveform-timing performance of the module by comparing with a 10 GS/s oscilloscope in a setup with plastic scintillators and fast PMTs. Different waveform timing algorithms are employed for analysis, and the module shows comparable timing performance with that of the oscilloscope.展开更多
This paper introduces a high-revolution,200kHz signal bandwidth EA modulator for low-IF GSM receivers that adopts a 2-1 cascaded single-bit structure to achieve high linearity and stability. Our design is realized in ...This paper introduces a high-revolution,200kHz signal bandwidth EA modulator for low-IF GSM receivers that adopts a 2-1 cascaded single-bit structure to achieve high linearity and stability. Our design is realized in a standard 0.18μm CMOS process with art active area of 0.5mm× 1.1mm.The EA modulator is driven by a single 19.2MHz clock signal and dissipates 5.88mW from 3V power supply. The experimental results show that,with an oversampling ratio of 48, the modulator achieves a 84.4dB dynamic range,73.8dB peak SNDR, and 80dB peak SNR in the signal bandwidth of 200kHz.展开更多
We have developed an electronic hardware system for the control and readout of multi-superconducting qubit devices.The hardware system is based on the design ideas of good scalability,high synchronization and low late...We have developed an electronic hardware system for the control and readout of multi-superconducting qubit devices.The hardware system is based on the design ideas of good scalability,high synchronization and low latency.The system,housed inside a VPX-6U chassis,includes multiple arbitrary-waveform generator(AWG)channels,analog-digital-converter(ADC)channels as well as direct current source channels.The system can be used for the control and readout of up to twelve superconducting transmon qubits in one chassis,and control and readout of more and more qubit can be carried out by interconnecting the chassis.By using field programmable gate array(FPGA)processors,the system incorporates three features that are specifically useful for superconducting qubit research.Firstly,qubit signals can be processed using the on-board FPGA after being acquired by ADCs,significantly reducing data processing time and data amount for storage and transmission.Secondly,different output modes,such as direct output and sequential output modes,of AWG can be implemented with pre-encoded FPGA.Thirdly,with data acquisition ADCs and control AWGs jointly controlled by the same FPGA,the feedback latency can be reduced,and in our test a 178.4 ns latency time is realized.This is very useful for future quantum feedback experiments.Finally,we demonstrate the functionality of the system by applying the system to the control and readout of a 10 qubit superconducting quantum processor.展开更多
文摘In mmWave massive multiple-input multiple-output(MIMO)communication systems,the extension of low-complexity narrowband precoding schemes to be operated on wideband systems under frequency-selective channels remains an important challenge at the current time.This paper investigates a low complexity wideband hybrid precoding scheme for mmWave massive MIMO multicarrier systems under a single-user,fully-connected hybrid architecture.We show that the radio frequency(RF)precoding/combining vectors can be directly derived from the eigenvectors of the optimal fully-digital covariance matrix over all subcarriers in order to maximize the sum rate of spectral efficiency.We also suggest a new method that iteratively reduces the residual error between the covariance matrix and the sum of products of precoding matrices over all the subcarriers to improve the performance in the case where the number of RF chains is higher than the number of streams.The results of the simulation show that the proposed schemes’complexity is low compared to the present methods,and their performance can almost reach the upper bound achieved by the optimal full-baseband design.
文摘Large number of antennas and higher bandwidth usage in massive multiple-input-multipleoutput(MIMO)systems create immense burden on receiver in terms of higher power consumption.The power consumption at the receiver radio frequency(RF)circuits can be significantly reduced by the application of analog-to-digital converter(ADC)of low resolution.In this paper we investigate bandwidth efficiency(BE)of massive MIMO with perfect channel state information(CSI)by applying low resolution ADCs with Rician fadings.We start our analysis by deriving the additive quantization noise model,which helps to understand the effects of ADC resolution on BE by keeping the power constraint at the receiver in radar.We also investigate deeply the effects of using higher bit rates and the number of BS antennas on bandwidth efficiency(BE)of the system.We emphasize that good bandwidth efficiency can be achieved by even using low resolution ADC by using regularized zero-forcing(RZF)combining algorithm.We also provide a generic analysis of energy efficiency(EE)with different options of bits by calculating the energy efficiencies(EE)using the achievable rates.We emphasize that satisfactory BE can be achieved by even using low-resolution ADC/DAC in massive MIMO.
基金Project supported by the Major Projects for the Core Electronic Devices,High-End General Chips and Basic Software Products(No. 2009ZX01031-002-008)
文摘An analog/digital reconfigurable automatic gain control （AGC） circuit with a novel DC offset cancel- lation circuit for a direct-conversion receiver is presented. The AGC is analog/digital reconfigurable in order to be compatible with different baseband chips. What＇s more, a novel DC offset cancellation （DCOC） circuit with an HPCF （high pass cutoff frequency） less than 10 kHz is proposed. The AGC is fabricated by a 0.18μm CMOS process. Under analog control mode, the AGC achieves a 70 dB dynamic range with a 3 dB-bandwidth larger than 60 MHz. Under digital control mode, through a 5-bit digital control word, the AGC shows a 64 dB gain control range by 2 dB each step with a gain error of less than 0.3 dB. The DC offset cancellation circuits can suppress the output DC offset voltage to be less than 1.5 mV, while the offset voltage of 40 mV is introduced into the input. The overall power consumption is less than 3.5 mA, and the die area is 800 ×300μm2.
文摘A continuously or/and discontinuously tunable LiNbO3 Optical Parametric Oscillator (OPO) with the spectral range of 1.42 - 4.24 um and shifting of 0…12 nm is created and investigated. The OPO resonator ring circuit provides for the radiation energy output value of up to 50 mJ. Radiation bandwidth narrowing of up to 0.7 cm–1 by introducing of the Fabry-Perot etalon into the OPO resonator has been obtained.
基金Supported by Knowledge Innovation Program of the Chinese Academy of Sciences(KJCX2-YW-N27)National Natural Science Foundation of China(11175176)
文摘We first clarify timing issues of non-uniform sampling intervals regarding a 5 GS/s fast pulse sampling module with DRS4. A calibration strategy is proposed, and as a result, the waveform timing performance is improved to below 10 ps RMS. We then further evaluate waveform-timing performance of the module by comparing with a 10 GS/s oscilloscope in a setup with plastic scintillators and fast PMTs. Different waveform timing algorithms are employed for analysis, and the module shows comparable timing performance with that of the oscilloscope.
文摘This paper introduces a high-revolution,200kHz signal bandwidth EA modulator for low-IF GSM receivers that adopts a 2-1 cascaded single-bit structure to achieve high linearity and stability. Our design is realized in a standard 0.18μm CMOS process with art active area of 0.5mm× 1.1mm.The EA modulator is driven by a single 19.2MHz clock signal and dissipates 5.88mW from 3V power supply. The experimental results show that,with an oversampling ratio of 48, the modulator achieves a 84.4dB dynamic range,73.8dB peak SNDR, and 80dB peak SNR in the signal bandwidth of 200kHz.
基金Project supported by the State Key Development Program for Basic Research of China(Grants Nos.2017YFA0304300 and 2016YFA0300600)the Natural Science Foundation of Beijing,China(Grant No.Z190012)+1 种基金the Key-Area Research and Development Program of Guangdong Province,China(Grant No.2020B0303030001)the Strategic Priority Research Program of Chinese Academy of Sciences(Grant No.XDB28000000).
文摘We have developed an electronic hardware system for the control and readout of multi-superconducting qubit devices.The hardware system is based on the design ideas of good scalability,high synchronization and low latency.The system,housed inside a VPX-6U chassis,includes multiple arbitrary-waveform generator(AWG)channels,analog-digital-converter(ADC)channels as well as direct current source channels.The system can be used for the control and readout of up to twelve superconducting transmon qubits in one chassis,and control and readout of more and more qubit can be carried out by interconnecting the chassis.By using field programmable gate array(FPGA)processors,the system incorporates three features that are specifically useful for superconducting qubit research.Firstly,qubit signals can be processed using the on-board FPGA after being acquired by ADCs,significantly reducing data processing time and data amount for storage and transmission.Secondly,different output modes,such as direct output and sequential output modes,of AWG can be implemented with pre-encoded FPGA.Thirdly,with data acquisition ADCs and control AWGs jointly controlled by the same FPGA,the feedback latency can be reduced,and in our test a 178.4 ns latency time is realized.This is very useful for future quantum feedback experiments.Finally,we demonstrate the functionality of the system by applying the system to the control and readout of a 10 qubit superconducting quantum processor.
