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A novel analog/digital reconfigurable automatic gain control with a novel DC offset cancellation circuit 被引量:1

A novel analog/digital reconfigurable automatic gain control with a novel DC offset cancellation circuit
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摘要 An analog/digital reconfigurable automatic gain control (AGC) circuit with a novel DC offset cancel- lation circuit for a direct-conversion receiver is presented. The AGC is analog/digital reconfigurable in order to be compatible with different baseband chips. What's more, a novel DC offset cancellation (DCOC) circuit with an HPCF (high pass cutoff frequency) less than 10 kHz is proposed. The AGC is fabricated by a 0.18μm CMOS process. Under analog control mode, the AGC achieves a 70 dB dynamic range with a 3 dB-bandwidth larger than 60 MHz. Under digital control mode, through a 5-bit digital control word, the AGC shows a 64 dB gain control range by 2 dB each step with a gain error of less than 0.3 dB. The DC offset cancellation circuits can suppress the output DC offset voltage to be less than 1.5 mV, while the offset voltage of 40 mV is introduced into the input. The overall power consumption is less than 3.5 mA, and the die area is 800 ×300μm2. An analog/digital reconfigurable automatic gain control (AGC) circuit with a novel DC offset cancel- lation circuit for a direct-conversion receiver is presented. The AGC is analog/digital reconfigurable in order to be compatible with different baseband chips. What's more, a novel DC offset cancellation (DCOC) circuit with an HPCF (high pass cutoff frequency) less than 10 kHz is proposed. The AGC is fabricated by a 0.18μm CMOS process. Under analog control mode, the AGC achieves a 70 dB dynamic range with a 3 dB-bandwidth larger than 60 MHz. Under digital control mode, through a 5-bit digital control word, the AGC shows a 64 dB gain control range by 2 dB each step with a gain error of less than 0.3 dB. The DC offset cancellation circuits can suppress the output DC offset voltage to be less than 1.5 mV, while the offset voltage of 40 mV is introduced into the input. The overall power consumption is less than 3.5 mA, and the die area is 800 ×300μm2.
出处 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2011年第2期79-84,共6页 半导体学报(英文版)
基金 Project supported by the Major Projects for the Core Electronic Devices,High-End General Chips and Basic Software Products(No. 2009ZX01031-002-008)
关键词 automatic gain control analog/digital reconfigurable DC offset cancellation automatic gain control analog/digital reconfigurable DC offset cancellation
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