本研究以学会专家姓名、职称、机构、发表论文及所属期刊等信息为数据源,以RDF格式存储在非关系型数据库Open Link Virtuoso中,并以开放的本体词表(DC、FOAF、BIBO等)为基础,扩展构建能满足系统需要的本体,基于此构建了具有推理分析功...本研究以学会专家姓名、职称、机构、发表论文及所属期刊等信息为数据源,以RDF格式存储在非关系型数据库Open Link Virtuoso中,并以开放的本体词表(DC、FOAF、BIBO等)为基础,扩展构建能满足系统需要的本体,基于此构建了具有推理分析功能、并以DOI号整合了pubmed文献数据的专家系统,本文详细阐释了构建过程中涉及的关联数据、语义推理等技术问题及解决方案。展开更多
随着当今电子行业的发展,对SoC芯片,尤其是数模混合芯片的要求越来越高。和传统的DEF/GDS数据交互方式相比,Mixed Signal Open Database(MSOA)RapidPDK可以帮助设计人员通过相同的PDK更好地完成数字工具Innovus和模拟工具Virtuoso之间...随着当今电子行业的发展,对SoC芯片,尤其是数模混合芯片的要求越来越高。和传统的DEF/GDS数据交互方式相比,Mixed Signal Open Database(MSOA)RapidPDK可以帮助设计人员通过相同的PDK更好地完成数字工具Innovus和模拟工具Virtuoso之间的数据传递。首先描述了5 nm MSOA RapidPDK生成方式,其次使用生成的PDK实现5 nm IP物理实现,同时验证MSOA flow对5 nm设计在版图完成和交付方面的速率提升。展开更多
ADE Verifier是Cadence New ADE家庭成员中的重要一员,它主要用于项目管理和验证。Verifier主要功能;(1)可以在I C设计项目中统一管理仿真case与指标对应关系,手动/自动刷新ADE的最新仿真结果并显示其指标通过情况;(2)还可以通过一键完...ADE Verifier是Cadence New ADE家庭成员中的重要一员,它主要用于项目管理和验证。Verifier主要功能;(1)可以在I C设计项目中统一管理仿真case与指标对应关系,手动/自动刷新ADE的最新仿真结果并显示其指标通过情况;(2)还可以通过一键完成项目所有仿真并以简明的界面给出仿真结果和spec达成与否等信息。(3)其流程具有高的统筹性,高效性,操作简单等优点。同时该流程能够提高项目设计规范性,仿真完备性,从而提高芯片设计成功率。本文针对海思公司一个实际ADC项目验证了Verifier flow,在整个流程中可以直观清晰查看整个项目各指标状态和达成情况;结合Matlab在New ADE的集成功能,调用Mat l ab计算的结果也可以直接在ADE和Verifier中显示,基本达到了一键完成所有仿真,大大降低了项目换代,项目管理和项目验证而投入的人力成本。展开更多
In the era of digital signal processing,like graphics and computation systems,multiplication-accumulation is one of the prime operations.A MAC unit is a vital component of a digital system,like different Fast Fourier ...In the era of digital signal processing,like graphics and computation systems,multiplication-accumulation is one of the prime operations.A MAC unit is a vital component of a digital system,like different Fast Fourier Transform(FFT)algorithms,convolution,image processing algorithms,etcetera.In the domain of digital signal processing,the use of normalization architecture is very vast.The main objective of using normalization is to performcomparison and shift operations.In this research paper,an evolutionary approach for designing an optimized normalization algorithm is proposed using basic logical blocks such as Multiplexer,Adder etc.The proposed normalization algorithm is further used in designing an 8×8 bit Signed Floating-Point Multiply-Accumulate(SFMAC)architecture.Since the SFMAC can accept an 8-bit significand and a 3-bit exponent,the input to the said architecture can be somewhere between−(7.96872)_(10) to+(7.96872)_(10).The proposed architecture is designed and implemented using the Cadence Virtuoso using 90 and 130 nm technologies(in Generic Process Design Kit(GPDK)and Taiwan Semiconductor Manufacturing Company(TSMC),respectively).To reduce the power consumption of the proposed normalization architecture,techniques such as“block enabling”and“clock gating”are used rigorously.According to the analysis done on Cadence,the proposed architecture uses the least amount of power compared to its current predecessors.展开更多
New methodologies for l-Bit XOR-XNOR full- adder circuits are proposed to improve the speed and power as these circuits are basic building blocks for ALU circuit implementation. This paper presents comparative study o...New methodologies for l-Bit XOR-XNOR full- adder circuits are proposed to improve the speed and power as these circuits are basic building blocks for ALU circuit implementation. This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Simulation results illustrate the superiority of the proposed adder circuit against the conventional complementary metal-oxide-semiconductor （CMOS）, complementary pass-transistor logic （CPL）, TG, and Hybrid adder circuits in terms of delay, power and power delay product （PDP）. Simulation results reveal that the proposed circuit exhibits lower PDP and is more power efficient and faster when compared with the best available 1-bit full adder circuits. The design is implemented on UMC 0.18 μm process models in Cadence Virtuoso Schematic Composer at 1.8 V single ended supply voltage and simulations are carried out on Spectre S.展开更多
文摘本研究以学会专家姓名、职称、机构、发表论文及所属期刊等信息为数据源,以RDF格式存储在非关系型数据库Open Link Virtuoso中,并以开放的本体词表(DC、FOAF、BIBO等)为基础,扩展构建能满足系统需要的本体,基于此构建了具有推理分析功能、并以DOI号整合了pubmed文献数据的专家系统,本文详细阐释了构建过程中涉及的关联数据、语义推理等技术问题及解决方案。
文摘ADE Verifier是Cadence New ADE家庭成员中的重要一员,它主要用于项目管理和验证。Verifier主要功能;(1)可以在I C设计项目中统一管理仿真case与指标对应关系,手动/自动刷新ADE的最新仿真结果并显示其指标通过情况;(2)还可以通过一键完成项目所有仿真并以简明的界面给出仿真结果和spec达成与否等信息。(3)其流程具有高的统筹性,高效性,操作简单等优点。同时该流程能够提高项目设计规范性,仿真完备性,从而提高芯片设计成功率。本文针对海思公司一个实际ADC项目验证了Verifier flow,在整个流程中可以直观清晰查看整个项目各指标状态和达成情况;结合Matlab在New ADE的集成功能,调用Mat l ab计算的结果也可以直接在ADE和Verifier中显示,基本达到了一键完成所有仿真,大大降低了项目换代,项目管理和项目验证而投入的人力成本。
基金This work was supported by Research Support Fund(RSF)of Symbiosis International(Deemed University),Pune,India。
文摘In the era of digital signal processing,like graphics and computation systems,multiplication-accumulation is one of the prime operations.A MAC unit is a vital component of a digital system,like different Fast Fourier Transform(FFT)algorithms,convolution,image processing algorithms,etcetera.In the domain of digital signal processing,the use of normalization architecture is very vast.The main objective of using normalization is to performcomparison and shift operations.In this research paper,an evolutionary approach for designing an optimized normalization algorithm is proposed using basic logical blocks such as Multiplexer,Adder etc.The proposed normalization algorithm is further used in designing an 8×8 bit Signed Floating-Point Multiply-Accumulate(SFMAC)architecture.Since the SFMAC can accept an 8-bit significand and a 3-bit exponent,the input to the said architecture can be somewhere between−(7.96872)_(10) to+(7.96872)_(10).The proposed architecture is designed and implemented using the Cadence Virtuoso using 90 and 130 nm technologies(in Generic Process Design Kit(GPDK)and Taiwan Semiconductor Manufacturing Company(TSMC),respectively).To reduce the power consumption of the proposed normalization architecture,techniques such as“block enabling”and“clock gating”are used rigorously.According to the analysis done on Cadence,the proposed architecture uses the least amount of power compared to its current predecessors.
文摘New methodologies for l-Bit XOR-XNOR full- adder circuits are proposed to improve the speed and power as these circuits are basic building blocks for ALU circuit implementation. This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Simulation results illustrate the superiority of the proposed adder circuit against the conventional complementary metal-oxide-semiconductor （CMOS）, complementary pass-transistor logic （CPL）, TG, and Hybrid adder circuits in terms of delay, power and power delay product （PDP）. Simulation results reveal that the proposed circuit exhibits lower PDP and is more power efficient and faster when compared with the best available 1-bit full adder circuits. The design is implemented on UMC 0.18 μm process models in Cadence Virtuoso Schematic Composer at 1.8 V single ended supply voltage and simulations are carried out on Spectre S.
