摘要
ADE Verifier是Cadence New ADE家庭成员中的重要一员,它主要用于项目管理和验证。Verifier主要功能;(1)可以在I C设计项目中统一管理仿真case与指标对应关系,手动/自动刷新ADE的最新仿真结果并显示其指标通过情况;(2)还可以通过一键完成项目所有仿真并以简明的界面给出仿真结果和spec达成与否等信息。(3)其流程具有高的统筹性,高效性,操作简单等优点。同时该流程能够提高项目设计规范性,仿真完备性,从而提高芯片设计成功率。本文针对海思公司一个实际ADC项目验证了Verifier flow,在整个流程中可以直观清晰查看整个项目各指标状态和达成情况;结合Matlab在New ADE的集成功能,调用Mat l ab计算的结果也可以直接在ADE和Verifier中显示,基本达到了一键完成所有仿真,大大降低了项目换代,项目管理和项目验证而投入的人力成本。
ADE Verifier is an important member in New ADE family. It’s usually used in project management and project verification. In IC design project we can uniformly manage matching relationship between simulation cases and their specs with Verifier which can manually or automatically refresh ADE’s simulation results and show pass/fail. We can finish all simulations in project just with clicking one button in Verifier which can also show the simulation results and pass/fail information. There’re many advantages with this flow, such as: high co-ordination, high efficiency and simple to use. Meanwhile it can improve normalization and verification completeness for a project. Consequently the success rate of a chip design is increased. This paper is related to Verifier flow with a real ADC project in Hisilicon. In the flow we can check all of the specs and reach status very clearly. With Matlab integrated in New ADE the results from Matlab can also be easily shown in ADE and Verifier, thus we almost finish all the simulations and get the specs pass status just with clicking a button. It greatly reduces the labor cost on project porting, management and verification.
作者
蒋佳君
黄志荣
吕波
孙金铎
JIANG Jia-Jun;HUANG Zhi-rong;LV Bob;SUN Jin-duo(Hisilicon;Cadence)
出处
《中国集成电路》
2019年第1期47-56,共10页
China lntegrated Circuit
基金
Cadence公司对本项目的巨大付出
