Semiconductor lasers,an important subfield of semiconductor photonics,have fundamentally changed many aspects of our lives and enabled many technologies since their creation in the 1960s.As in other semiconductor-base...Semiconductor lasers,an important subfield of semiconductor photonics,have fundamentally changed many aspects of our lives and enabled many technologies since their creation in the 1960s.As in other semiconductor-based fields,such as microelectronics,miniaturization has been a constant theme,with nanolasers being an important frontier of research over the last decade.We review the progress,existing issues,and future prospects of nanolasers,especially in relation to their potential application in chip-scale optical interconnects.One of the important challenges in this application is minimizing the size and energy consumption of nanolasers.We begin with the application background of this challenge and then compare basic features of various semiconductor lasers.We present existing issues with nanolasers and discuss potential solutions to meet the size and energy-efficiency challenge.Our discussions cover a broad range of miniaturized lasers,including plasmonic nanolasers and lasers with two-dimensional monolayer gain materials,with focus on near-infrared wavelengths.展开更多
The effects of Bi addition on the growth of intermetallic compound (IMC) formation in Sn-3.8Ag-0.7Cu solder joints were investigated. The test samples were prepared by conventional surface mounting technology. To inve...The effects of Bi addition on the growth of intermetallic compound (IMC) formation in Sn-3.8Ag-0.7Cu solder joints were investigated. The test samples were prepared by conventional surface mounting technology. To investigate the element diffusion and the growth kinetics of intermetallics formation in solder joint, isothermal aging test was performed at temperatures of 100, 150, and 190℃, respectively. The optical microscope (OM) and scanning electron microscope (SEM) were used to observe microstructure evolution of solder joint and to estimate the thickness and the grain size of the intermetallic layers. The IMC phases were identified by energy dispersive X-ray (EDX) and X-ray diffractometer (XRD). The results clearly show that adding about 1.0% Bi in Sn-Ag-Cu solder alloy system can refine the grain size of the IMC and inhibit the excessive IMC growth in solder joints, and therefore improve the reliability of the Pb-free solder joints. Through observation of the microstructural evolution of the solder joints, the mechanism of inhibition of IMC growth due to Bi addition was proposed.展开更多
The arrival of the big data era has driven the rapid development of high-speed optical signaling and processing, ranging from long-haul optical communication links to short-reach data centers and highperformance compu...The arrival of the big data era has driven the rapid development of high-speed optical signaling and processing, ranging from long-haul optical communication links to short-reach data centers and highperformance computing, and even micro-/nano-scale inter-chip and intra-chip optical interconnects.On-chip photonic signaling is essential for optical data transmission, especially for chip-scale optical interconnects, while on-chip photonic processing is a critical technology for optical data manipulation or processing, especially at the network nodes to facilitate ultracompact data management with low power consumption. In this paper, we review recent research progress in on-chip photonic signaling and processing on silicon photonics platforms. Firstly, basic key devices (lasers, modulators, detectors)are introduced. Secondly, for on-chip photonic signaling, we present recent works on on-chip data transmission of advanced multi-level modulation signals using various silicon photonic integrated devices(microring, slot waveguide, hybrid plasmonic waveguide, subwavelength grating slot waveguide).Thirdly, for on-chip photonic processing, we summarize recent works on on-chip data processing of advanced multi-level modulation signals exploiting linear and nonlinear effects in different kinds of silicon photonic integrated devices (strip waveguide, directional coupler, 2D grating coupler, microring,silicon-organic hybrid slot waveguide). Various photonic processing functions are demonstrated, such as photonic switch, filtering, polarization/wavelength/mode (de)multiplexing, wavelength conversion,signal regeneration, optical logic and computing. Additionally, we also introduce extended silicon+photonics and show recent works on on-chip graphene-silicon photonic signal processing. The advances in on-chip silicon photonic signaling and processing with favorable performance pave the way to integrate complete optical communication systems on a monolithic chip and integrate silicon photonics and silicon nanoelectronics on a chip展开更多
Explosive growth in demand for data traffic has prompted exploration of the spatial dimension of lightwaves, which provides a degree of freedom to expand data transmission capacity. Various techniques basedon bulky op...Explosive growth in demand for data traffic has prompted exploration of the spatial dimension of lightwaves, which provides a degree of freedom to expand data transmission capacity. Various techniques basedon bulky optical devices have been proposed to tailor light waves in the spatial dimension. However, theirinherent large size, extra loss, and precise alignment requirements make these techniques relativelydifficult to implement in a compact and flexible way. In contrast, three-dimensional (3D) photonic chips withcompact size and low loss provide a promising miniaturized candidate for tailoring light in the spatialdimension. Significantly, they are attractive for chip-assisted short-distance spatial mode optical interconnectsthat are challenging to bulky optics. Here, we propose and fabricate femtosecond laser-inscribed 3D photonicchips to tailor orbital angular momentum (OAM) modes in the spatial dimension. Various functions on theplatform of 3D photonic chips are experimentally demonstrated, including the generation, (de)multiplexing,and exchange of OAM modes. Moreover, chip-chip and chip–fiber–chip short-distance optical interconnectsusing OAM modes are demonstrated in the experiment with favorable performance. This work paves the wayto flexibly tailor light waves on 3D photonic chips and offers a compact solution for versatile opticalinterconnects and other emerging applications with spatial modes.展开更多
Physical vapor deposition(PVD)can be used to produce high-quality Gd_(2)O_(3)-doped CeO2(GDC)films.Among various PVD methods,reactive sputtering provides unique benefits,such as high deposition rates and easy upscalin...Physical vapor deposition(PVD)can be used to produce high-quality Gd_(2)O_(3)-doped CeO2(GDC)films.Among various PVD methods,reactive sputtering provides unique benefits,such as high deposition rates and easy upscaling for industrial applications.GDC thin films were successfully fabricated through reactive sputtering using a Gd_(0.2)Ce_(0.8)(at%)metallic target,and their application in solid oxide fuel cells,such as buffer layers between yttria-stabilized zirconia(YSZ)/La0.6Sr0.4Co0.2Fe0.8O_(3−δ)and as sublayers in the steel/coating system,was evaluated.First,the direct current(DC)reactive-sputtering behavior of the GdCe metallic target was determined.Then,the GDC films were deposited on NiO-YSZ/YSZ half-cells to investigate the influence of oxygen flow rate on the quality of annealed GDC films.The results demonstrated that reactive sputtering can be used to prepare thin and dense GDC buffer layers without high-temperature sintering.Furthermore,the cells with a sputtered GDC buffer layer showed better electrochemical performance than those with a screen-printed GDC buffer layer.In addition,the insertion of a GDC sublayer between the SUS441 interconnects and the Mn-Co spinel coatings contributed to the reduction of the oxidation rate for SUS441 at operating temperatures,according to the area-specific resistance tests.展开更多
We demonstrate a sub-nanosecond electro-optical switch with low crosstalk in a silicon-on-insulator （SOI） dual-coupled micro-ring embedded with p-i-n diodes. A crosstalk of -23 dB is obtained in the 20-μm-radius mi...We demonstrate a sub-nanosecond electro-optical switch with low crosstalk in a silicon-on-insulator （SOI） dual-coupled micro-ring embedded with p-i-n diodes. A crosstalk of -23 dB is obtained in the 20-μm-radius micro-ring with the well-designing asymmetric dual-coupling structure. By optimizations of the doping profiles and the fabrication processes, the sub-nanosecond switch-on/off time of 〈400 ps is finally realized under an electrical pre-emphasized driving signal. This compact and fast-response micro-ring switch, which can be fabricated by complementary metal oxide semiconductor （CMOS） compatible technologies, have enormous potential in optical interconnects of multicore networks-on-chip.展开更多
The vertical cavity surface emitting laser (VCSEL) arrays and VCSEL-based optical transmission modules are investigated.It includes the VCSEL's spectral characteristic,modulation characteristic,high frequency char...The vertical cavity surface emitting laser (VCSEL) arrays and VCSEL-based optical transmission modules are investigated.It includes the VCSEL's spectral characteristic,modulation characteristic,high frequency characteristic,and compatibility with microelectronic circuit.The module consists of 1×16 VCSEL array and 16-channel lasers driver with 0.35μm CMOS circuit by hybrid integration.During the test process,the module operates well at more than 2GHz in -3dB frequency bandwidth.展开更多
An optical waveguide interconnect mesh network scheme for parallel multiprocessor systems based on an electro-optical printed circuit board （EOPCB） with multimode polymer waveguide is proposed. The system consists o...An optical waveguide interconnect mesh network scheme for parallel multiprocessor systems based on an electro-optical printed circuit board （EOPCB） with multimode polymer waveguide is proposed. The system consists of 2×2 processor element chips interconnected in a mesh network configuration. An additional layer with optical waveguide structure is embedded in a conventional printed circuit board to construct the EOPCB. Vertical cavity surface emitting laser （VCSEL）/positive intrinsic-negative （PIN） arrays are ap- plied as the optical transmitters/receivers. Three 1 ~ 12 VCSEL/PIN parallel optical transmitting/receiving modules are used to provide 32 input/output optical channels required by the 2~2 chip-to-chip optical mesh interconnect system. The data rate in each optical channel is 3.125 Gbps and thus 10 Gbps parallel optical interconnect link for each direction of a chip is obtained. The optical signals from a processor element chip can be transmitted to another chip through optical waveguide interconnect embedded in the board. Thus the optical interconnect mesh network for parallel multiprocessor system can be implemented.展开更多
SUS430 （16% - 17% （mass fraction） Cr） can be used as interconnects for solid oxide fuel cells （SOFCs） that operate at lower temperatures （ 〈 800 ℃ ）. However, oxidation of steel can occur readily at elevated...SUS430 （16% - 17% （mass fraction） Cr） can be used as interconnects for solid oxide fuel cells （SOFCs） that operate at lower temperatures （ 〈 800 ℃ ）. However, oxidation of steel can occur readily at elevated temperatures leading to the formation of Cr2O3 and spinel （Fe3O4） and thus greatly degrades the performance of the fuel cell. The aim of this work was to reduce oxide growth, in particular, the Cr2O3 phase, through the application of La0.8Sr0.2MnO3-δ （LSM2O） and La0.8Sr0.2FeO3-δ（LSF20） coatings by atmospheric plasma spraying technology （APS）. Oxide growth was characterized by using X-ray diffraction （XRD）, scanning electron microscopy （SEM） with an energy dispersive X-ray （EDX） analyzer. During oxidation of fifty 20 h cycles at 800 ℃ in air, the samples with coatings remained very stable, whereas significant spallation and weight loss were observed for the uncoated steel. LSF20 presents apparently advantages in reducing oxidation growth, interface resistance and inhibition of diffusion of chromium. After exposure in air at 800 ℃ for 1000 h, the interfacial resistance of LSF20-coated alloy is lowered by more than 23 times to that of LSM20-coated layer.展开更多
The performance of high density chips operating in the GHz range is mostly affected by on-chip interconnects. The interconnect delay depends on many factors, a few of them are inputs toggling patterns, line ＆ couplin...The performance of high density chips operating in the GHz range is mostly affected by on-chip interconnects. The interconnect delay depends on many factors, a few of them are inputs toggling patterns, line ＆ coupling parasitics, input rise/fall time and source/load characteristics. The transition time of the input is of prime importance in high speed circuits. This paper addresses the FDTD based analysis of transition time effects on functional and dynamic crosstalk. The analysis is carried out for equal and unequal transition times of coupled inputs. The analysis of the effects of unequal rise time is equally important because practically, it is quite common to have mismatching in the rise time of the signals transmitting through different length wires. To demonstrate the effects, two distributed RLC lines coupled inductively and capacitively are taken into consideration. The FDTD technique is used because it gives accurate results and carries time domain analysis of coupled lines. The number of lumps in SPICE simulations is considered the same as those of spatial segments. To validate the FDTD computed results, SPICE simulations are run and results are compared. A good agreement of the computed results has been observed with respect to SPICE simulated results. An average error of less than 3.2% is observed in the computation of the performance parameters using the proposed method.展开更多
Based on the heat diffusion equation of multilevel interconnects, a novel analytical thermal model for multilevel nano-scale interconnects considering the via effect is presented, which can compute quickly the tempera...Based on the heat diffusion equation of multilevel interconnects, a novel analytical thermal model for multilevel nano-scale interconnects considering the via effect is presented, which can compute quickly the temperature of multilevel interconnects, with substrate temperature given. Based on the proposed model and the 65 nm complementary metal oxide semiconductor （CMOS） process parameter, the temperature of nano-scale interconnects is computed. The computed results show that the via effect has a great effect on local interconnects, but the reduction of thermal conductivity has little effect on local interconnects. With the reduction of thermal conductivity or the increase of current density, however, the temperature of global interconnects rises greatly, which can result in a great deterioration in their performance. The proposed model can be applied to computer aided design （CAD） of very large-scale integrated circuits （VLSIs） in nano-scale technologies.展开更多
基金The author acknowledges funding support from the National Natural Science Foundation of China under Key Research Program“New Physics and Control of Light Field”(No.91750206)from Tsinghua University,from the Beijing National Research Center for Information Technology,the Beijing Innovation Center of Future Chips.
文摘Semiconductor lasers,an important subfield of semiconductor photonics,have fundamentally changed many aspects of our lives and enabled many technologies since their creation in the 1960s.As in other semiconductor-based fields,such as microelectronics,miniaturization has been a constant theme,with nanolasers being an important frontier of research over the last decade.We review the progress,existing issues,and future prospects of nanolasers,especially in relation to their potential application in chip-scale optical interconnects.One of the important challenges in this application is minimizing the size and energy consumption of nanolasers.We begin with the application background of this challenge and then compare basic features of various semiconductor lasers.We present existing issues with nanolasers and discuss potential solutions to meet the size and energy-efficiency challenge.Our discussions cover a broad range of miniaturized lasers,including plasmonic nanolasers and lasers with two-dimensional monolayer gain materials,with focus on near-infrared wavelengths.
文摘The effects of Bi addition on the growth of intermetallic compound (IMC) formation in Sn-3.8Ag-0.7Cu solder joints were investigated. The test samples were prepared by conventional surface mounting technology. To investigate the element diffusion and the growth kinetics of intermetallics formation in solder joint, isothermal aging test was performed at temperatures of 100, 150, and 190℃, respectively. The optical microscope (OM) and scanning electron microscope (SEM) were used to observe microstructure evolution of solder joint and to estimate the thickness and the grain size of the intermetallic layers. The IMC phases were identified by energy dispersive X-ray (EDX) and X-ray diffractometer (XRD). The results clearly show that adding about 1.0% Bi in Sn-Ag-Cu solder alloy system can refine the grain size of the IMC and inhibit the excessive IMC growth in solder joints, and therefore improve the reliability of the Pb-free solder joints. Through observation of the microstructural evolution of the solder joints, the mechanism of inhibition of IMC growth due to Bi addition was proposed.
基金supported by the National Program for Support of Top-notch Young Professionalsthe National Natural Science Foundation of China(NSFC)(61222502,61761130082,11574001and 11774116)+5 种基金the Royal Society-Newton Advanced Fellowshipthe National Basic Research Program of China(973 Program)(2014CB340004)the Yangtze River Excellent Young Scholars Programthe Program for New Century Excellent Talents in University(NCET-11-0182)the Natural Science Foundation of Hubei Province of China(2018CFA048)the Program for HUST Academic Frontier Youth Team
文摘The arrival of the big data era has driven the rapid development of high-speed optical signaling and processing, ranging from long-haul optical communication links to short-reach data centers and highperformance computing, and even micro-/nano-scale inter-chip and intra-chip optical interconnects.On-chip photonic signaling is essential for optical data transmission, especially for chip-scale optical interconnects, while on-chip photonic processing is a critical technology for optical data manipulation or processing, especially at the network nodes to facilitate ultracompact data management with low power consumption. In this paper, we review recent research progress in on-chip photonic signaling and processing on silicon photonics platforms. Firstly, basic key devices (lasers, modulators, detectors)are introduced. Secondly, for on-chip photonic signaling, we present recent works on on-chip data transmission of advanced multi-level modulation signals using various silicon photonic integrated devices(microring, slot waveguide, hybrid plasmonic waveguide, subwavelength grating slot waveguide).Thirdly, for on-chip photonic processing, we summarize recent works on on-chip data processing of advanced multi-level modulation signals exploiting linear and nonlinear effects in different kinds of silicon photonic integrated devices (strip waveguide, directional coupler, 2D grating coupler, microring,silicon-organic hybrid slot waveguide). Various photonic processing functions are demonstrated, such as photonic switch, filtering, polarization/wavelength/mode (de)multiplexing, wavelength conversion,signal regeneration, optical logic and computing. Additionally, we also introduce extended silicon+photonics and show recent works on on-chip graphene-silicon photonic signal processing. The advances in on-chip silicon photonic signaling and processing with favorable performance pave the way to integrate complete optical communication systems on a monolithic chip and integrate silicon photonics and silicon nanoelectronics on a chip
基金This work was supported by the National Natural Science Foundation of China(Grant Nos.62125503 and 62261160388)the Key R&D Program of Hubei Province of China(Grant Nos.2020BAB001 and 2021BAA024)+2 种基金the Key R&D Program of Guangdong Province(Grant No.2018B030325002)the Shenzhen Science and Technology Program(Grant No.JCYJ20200109114018750)the Innovation Project of Optics Valley Laboratory(Grant No.OVL2021BG004).
文摘Explosive growth in demand for data traffic has prompted exploration of the spatial dimension of lightwaves, which provides a degree of freedom to expand data transmission capacity. Various techniques basedon bulky optical devices have been proposed to tailor light waves in the spatial dimension. However, theirinherent large size, extra loss, and precise alignment requirements make these techniques relativelydifficult to implement in a compact and flexible way. In contrast, three-dimensional (3D) photonic chips withcompact size and low loss provide a promising miniaturized candidate for tailoring light in the spatialdimension. Significantly, they are attractive for chip-assisted short-distance spatial mode optical interconnectsthat are challenging to bulky optics. Here, we propose and fabricate femtosecond laser-inscribed 3D photonicchips to tailor orbital angular momentum (OAM) modes in the spatial dimension. Various functions on theplatform of 3D photonic chips are experimentally demonstrated, including the generation, (de)multiplexing,and exchange of OAM modes. Moreover, chip-chip and chip–fiber–chip short-distance optical interconnectsusing OAM modes are demonstrated in the experiment with favorable performance. This work paves the wayto flexibly tailor light waves on 3D photonic chips and offers a compact solution for versatile opticalinterconnects and other emerging applications with spatial modes.
基金financially supported by the National Key R&D Program of China (No. 2018YFB1502203-1)the Guangdong Basic and Applied Basic Research Foundation (No. 2021B1515120087)the Stable Supporting Fund of Shenzhen, China (No. GXWD20201230155427003-202007 28114835006)
文摘Physical vapor deposition(PVD)can be used to produce high-quality Gd_(2)O_(3)-doped CeO2(GDC)films.Among various PVD methods,reactive sputtering provides unique benefits,such as high deposition rates and easy upscaling for industrial applications.GDC thin films were successfully fabricated through reactive sputtering using a Gd_(0.2)Ce_(0.8)(at%)metallic target,and their application in solid oxide fuel cells,such as buffer layers between yttria-stabilized zirconia(YSZ)/La0.6Sr0.4Co0.2Fe0.8O_(3−δ)and as sublayers in the steel/coating system,was evaluated.First,the direct current(DC)reactive-sputtering behavior of the GdCe metallic target was determined.Then,the GDC films were deposited on NiO-YSZ/YSZ half-cells to investigate the influence of oxygen flow rate on the quality of annealed GDC films.The results demonstrated that reactive sputtering can be used to prepare thin and dense GDC buffer layers without high-temperature sintering.Furthermore,the cells with a sputtered GDC buffer layer showed better electrochemical performance than those with a screen-printed GDC buffer layer.In addition,the insertion of a GDC sublayer between the SUS441 interconnects and the Mn-Co spinel coatings contributed to the reduction of the oxidation rate for SUS441 at operating temperatures,according to the area-specific resistance tests.
基金supported by the State Key Development Program for Basic Research of China(No. 2006CB302803)the National Natural Science Foundation of China(No.60877036)
文摘We demonstrate a sub-nanosecond electro-optical switch with low crosstalk in a silicon-on-insulator （SOI） dual-coupled micro-ring embedded with p-i-n diodes. A crosstalk of -23 dB is obtained in the 20-μm-radius micro-ring with the well-designing asymmetric dual-coupling structure. By optimizations of the doping profiles and the fabrication processes, the sub-nanosecond switch-on/off time of 〈400 ps is finally realized under an electrical pre-emphasized driving signal. This compact and fast-response micro-ring switch, which can be fabricated by complementary metal oxide semiconductor （CMOS） compatible technologies, have enormous potential in optical interconnects of multicore networks-on-chip.
文摘The vertical cavity surface emitting laser (VCSEL) arrays and VCSEL-based optical transmission modules are investigated.It includes the VCSEL's spectral characteristic,modulation characteristic,high frequency characteristic,and compatibility with microelectronic circuit.The module consists of 1×16 VCSEL array and 16-channel lasers driver with 0.35μm CMOS circuit by hybrid integration.During the test process,the module operates well at more than 2GHz in -3dB frequency bandwidth.
基金supported by the National Natural Science Foundation of China(No.60677023)the National"863"Program of China(No.2006AA01Z240).
文摘An optical waveguide interconnect mesh network scheme for parallel multiprocessor systems based on an electro-optical printed circuit board （EOPCB） with multimode polymer waveguide is proposed. The system consists of 2×2 processor element chips interconnected in a mesh network configuration. An additional layer with optical waveguide structure is embedded in a conventional printed circuit board to construct the EOPCB. Vertical cavity surface emitting laser （VCSEL）/positive intrinsic-negative （PIN） arrays are ap- plied as the optical transmitters/receivers. Three 1 ~ 12 VCSEL/PIN parallel optical transmitting/receiving modules are used to provide 32 input/output optical channels required by the 2~2 chip-to-chip optical mesh interconnect system. The data rate in each optical channel is 3.125 Gbps and thus 10 Gbps parallel optical interconnect link for each direction of a chip is obtained. The optical signals from a processor element chip can be transmitted to another chip through optical waveguide interconnect embedded in the board. Thus the optical interconnect mesh network for parallel multiprocessor system can be implemented.
文摘SUS430 （16% - 17% （mass fraction） Cr） can be used as interconnects for solid oxide fuel cells （SOFCs） that operate at lower temperatures （ 〈 800 ℃ ）. However, oxidation of steel can occur readily at elevated temperatures leading to the formation of Cr2O3 and spinel （Fe3O4） and thus greatly degrades the performance of the fuel cell. The aim of this work was to reduce oxide growth, in particular, the Cr2O3 phase, through the application of La0.8Sr0.2MnO3-δ （LSM2O） and La0.8Sr0.2FeO3-δ（LSF20） coatings by atmospheric plasma spraying technology （APS）. Oxide growth was characterized by using X-ray diffraction （XRD）, scanning electron microscopy （SEM） with an energy dispersive X-ray （EDX） analyzer. During oxidation of fifty 20 h cycles at 800 ℃ in air, the samples with coatings remained very stable, whereas significant spallation and weight loss were observed for the uncoated steel. LSF20 presents apparently advantages in reducing oxidation growth, interface resistance and inhibition of diffusion of chromium. After exposure in air at 800 ℃ for 1000 h, the interfacial resistance of LSF20-coated alloy is lowered by more than 23 times to that of LSM20-coated layer.
文摘The performance of high density chips operating in the GHz range is mostly affected by on-chip interconnects. The interconnect delay depends on many factors, a few of them are inputs toggling patterns, line ＆ coupling parasitics, input rise/fall time and source/load characteristics. The transition time of the input is of prime importance in high speed circuits. This paper addresses the FDTD based analysis of transition time effects on functional and dynamic crosstalk. The analysis is carried out for equal and unequal transition times of coupled inputs. The analysis of the effects of unequal rise time is equally important because practically, it is quite common to have mismatching in the rise time of the signals transmitting through different length wires. To demonstrate the effects, two distributed RLC lines coupled inductively and capacitively are taken into consideration. The FDTD technique is used because it gives accurate results and carries time domain analysis of coupled lines. The number of lumps in SPICE simulations is considered the same as those of spatial segments. To validate the FDTD computed results, SPICE simulations are run and results are compared. A good agreement of the computed results has been observed with respect to SPICE simulated results. An average error of less than 3.2% is observed in the computation of the performance parameters using the proposed method.
基金Project supported by the National Natural Science Foundation of China (Grant Nos 60676009 and 60725415)the National High Technology Research and Development Program of China (Grant Nos 2009AA01Z258 and 2009AA01Z260)
文摘Based on the heat diffusion equation of multilevel interconnects, a novel analytical thermal model for multilevel nano-scale interconnects considering the via effect is presented, which can compute quickly the temperature of multilevel interconnects, with substrate temperature given. Based on the proposed model and the 65 nm complementary metal oxide semiconductor （CMOS） process parameter, the temperature of nano-scale interconnects is computed. The computed results show that the via effect has a great effect on local interconnects, but the reduction of thermal conductivity has little effect on local interconnects. With the reduction of thermal conductivity or the increase of current density, however, the temperature of global interconnects rises greatly, which can result in a great deterioration in their performance. The proposed model can be applied to computer aided design （CAD） of very large-scale integrated circuits （VLSIs） in nano-scale technologies.
