The Rosenbrock function optimization belongs to unconstrained optimization problems, and its global minimum value is located at the bottom of a smooth and narrow valley of the parabolic shape. It is very difficult to ...The Rosenbrock function optimization belongs to unconstrained optimization problems, and its global minimum value is located at the bottom of a smooth and narrow valley of the parabolic shape. It is very difficult to find the global minimum value of the function because of the little information provided for the optimization algorithm. According to the characteristics of the Rosenbrock function, this paper specifically proposed an improved differential evolution algorithm that adopts the self-adaptive scaling factor F and crossover rate CR with elimination mechanism, which can effectively avoid premature convergence of the algorithm and local optimum. This algorithm can also expand the search range at an early stage to find the global minimum of the Rosenbrock function. Many experimental results show that the algorithm has good performance of function optimization and provides a new idea for optimization problems similar to the Rosenbrock function for some problems of special fields.展开更多
A virtual reconfigurable architecture(VRA)-based evolvable hardware is proposed for automatic synthesis of combinational logic circuits at gate-level.The proposed VRA is implemented by a Celoxica RC1000 peripheral com...A virtual reconfigurable architecture(VRA)-based evolvable hardware is proposed for automatic synthesis of combinational logic circuits at gate-level.The proposed VRA is implemented by a Celoxica RC1000 peripheral component interconnect(PCI)board with an Xilinx Virtex xcv2000E field programmable gate array(FPGA).To improve the quality of the evolved circuits,the VRA works through a two-stage evolution: finding a functional circuit and minimizing the number of logic gates used in a feasible circuit.To optimize the algorithm performance in the two-stage evolutionary process and set free the user from the time-consuming process of mutation parameter tuning,a self-adaptive mutation rate control(SAMRC)scheme is introduced.In the evolutionary process,the mutation rate control parameters are encoded as additional genes in the chromosome and also undergo evolutionary operations.The efficiency of the proposed methodology is tested with the evolutions of a 4-bit even parity function,a 2-bit multiplier,and a 3-bit multiplier.The obtained results demonstrate that our scheme improves the evolutionary design of combinational logic circuits in terms of quality of the evolved circuit as well as the computational effort,when compared to the existing evolvable hardware approaches.展开更多
文摘The Rosenbrock function optimization belongs to unconstrained optimization problems, and its global minimum value is located at the bottom of a smooth and narrow valley of the parabolic shape. It is very difficult to find the global minimum value of the function because of the little information provided for the optimization algorithm. According to the characteristics of the Rosenbrock function, this paper specifically proposed an improved differential evolution algorithm that adopts the self-adaptive scaling factor F and crossover rate CR with elimination mechanism, which can effectively avoid premature convergence of the algorithm and local optimum. This algorithm can also expand the search range at an early stage to find the global minimum of the Rosenbrock function. Many experimental results show that the algorithm has good performance of function optimization and provides a new idea for optimization problems similar to the Rosenbrock function for some problems of special fields.
基金Projects(61203308,61309014)supported by the National Natural Science Foundation of China
文摘A virtual reconfigurable architecture(VRA)-based evolvable hardware is proposed for automatic synthesis of combinational logic circuits at gate-level.The proposed VRA is implemented by a Celoxica RC1000 peripheral component interconnect(PCI)board with an Xilinx Virtex xcv2000E field programmable gate array(FPGA).To improve the quality of the evolved circuits,the VRA works through a two-stage evolution: finding a functional circuit and minimizing the number of logic gates used in a feasible circuit.To optimize the algorithm performance in the two-stage evolutionary process and set free the user from the time-consuming process of mutation parameter tuning,a self-adaptive mutation rate control(SAMRC)scheme is introduced.In the evolutionary process,the mutation rate control parameters are encoded as additional genes in the chromosome and also undergo evolutionary operations.The efficiency of the proposed methodology is tested with the evolutions of a 4-bit even parity function,a 2-bit multiplier,and a 3-bit multiplier.The obtained results demonstrate that our scheme improves the evolutionary design of combinational logic circuits in terms of quality of the evolved circuit as well as the computational effort,when compared to the existing evolvable hardware approaches.
