为了研究Ga N开关类功率放大器（PA）的温度特性,通过开展一系列的温度测试来研究温度变化对该Ga N PA各个性能参数的具体影响。测试结果表明：首先,较高的温度（〉80℃）会使Ga N HEMT的电特性发生严重恶化,进而导致器件的性能和可靠...为了研究Ga N开关类功率放大器（PA）的温度特性,通过开展一系列的温度测试来研究温度变化对该Ga N PA各个性能参数的具体影响。测试结果表明：首先,较高的温度（〉80℃）会使Ga N HEMT的电特性发生严重恶化,进而导致器件的性能和可靠性显著下降。其次,对于该开关类Ga N PA来说,随着温度的持续升高,其功率附加效率（PAE）显著降低,不能再保持高效率。而且,随着温度的突变和冲击次数的增加,电路出现显著的退化甚至失效。这些都说明了温度的变化对PA的性能产生了很大的影响,开关类PA对温度的变化非常敏感,而且温度冲击对其性能影响更为显著。这些研究为PA的可靠性设计提供了重要指导。展开更多
A novel design and optimization method for distributed amplifiers(DAs)is proposed to make the circuit design more convenient and efficient.This method combines artificial intelligence(AI)optimization with manual desig...A novel design and optimization method for distributed amplifiers(DAs)is proposed to make the circuit design more convenient and efficient.This method combines artificial intelligence(AI)optimization with manual design by two loops,i.e.,outer manual loop and inner AI loop.The layout design is followed by AI optimization to take more influencing factors such as parasitic effect into account for the practicability.A DA with three gain cells is designed and optimized in a standard 0.18μm complementary metal-oxide-semiconductor(CMOS)technology to verify the proposed method.With a chip area of only 0.55 mm2,the DA provides 9.8 dB average forward gain from 1 to 15.2 GHz.The output power at 1 dB output compression point is more than 7.7 dBm in the 2-14 GHz frequency band and the peak power-added efficiency(PAE)is 10.6%.The measurement results validate the proposed method as a robust DA design procedure for improving circuit performance and design efficiency.展开更多
基于IBM SOI 0.18μm CMOS工艺,设计了一种高功率附加效率(PAE)的E类功率放大器,由驱动级和输出级两级构成。驱动级采用E类结构,使输出级能更好地实现开与关。输出级采用电感谐振寄生电容,提高了效率。输出级的共栅管采用自偏置的方式,...基于IBM SOI 0.18μm CMOS工艺,设计了一种高功率附加效率(PAE)的E类功率放大器,由驱动级和输出级两级构成。驱动级采用E类结构,使输出级能更好地实现开与关。输出级采用电感谐振寄生电容,提高了效率。输出级的共栅管采用自偏置的方式,防止晶体管被击穿。两级之间使用了改善输出级电压和电流交叠的网络。仿真结果表明,在2.8 V电源电压下,工作频率为2.4 GHz时,功率放大器的输出功率为23.17 d Bm,PAE为57.7%。展开更多
This paper presents a new topology to implement Class F power amplifier for eliminating the on-resistance (R_(ON))effect.The time-domain and frequency-domain voltage and current waveforms for Class F amplifier are ana...This paper presents a new topology to implement Class F power amplifier for eliminating the on-resistance (R_(ON))effect.The time-domain and frequency-domain voltage and current waveforms for Class F amplifier are ana- lyzed using Fourier series analysis method.Considering the on-resistance effect,the formulas of the efficiency,output power,dc power dissipation,and fundamental load impedance are given from ideal current and voltage waveforms.For experimental verification,we designed and implemented a Class F power amplifier,which operates at 850 MHz using MGaAs/GaAs Heterostructure FET(HFET)device,and analyzed the measurement results.Test results show that the maximum PAE of 67% can be achieved at 28 dBm output power level.展开更多
文摘为了研究Ga N开关类功率放大器（PA）的温度特性,通过开展一系列的温度测试来研究温度变化对该Ga N PA各个性能参数的具体影响。测试结果表明：首先,较高的温度（〉80℃）会使Ga N HEMT的电特性发生严重恶化,进而导致器件的性能和可靠性显著下降。其次,对于该开关类Ga N PA来说,随着温度的持续升高,其功率附加效率（PAE）显著降低,不能再保持高效率。而且,随着温度的突变和冲击次数的增加,电路出现显著的退化甚至失效。这些都说明了温度的变化对PA的性能产生了很大的影响,开关类PA对温度的变化非常敏感,而且温度冲击对其性能影响更为显著。这些研究为PA的可靠性设计提供了重要指导。
基金the National Natural Science Foundation of China(No.61106021)the Natural Science Foundation of Jiangsu Province(No.BK20161072)the Research Fund of Nanjing University of Posts and Telecommunications(No.NY218051)
文摘A novel design and optimization method for distributed amplifiers(DAs)is proposed to make the circuit design more convenient and efficient.This method combines artificial intelligence(AI)optimization with manual design by two loops,i.e.,outer manual loop and inner AI loop.The layout design is followed by AI optimization to take more influencing factors such as parasitic effect into account for the practicability.A DA with three gain cells is designed and optimized in a standard 0.18μm complementary metal-oxide-semiconductor(CMOS)technology to verify the proposed method.With a chip area of only 0.55 mm2,the DA provides 9.8 dB average forward gain from 1 to 15.2 GHz.The output power at 1 dB output compression point is more than 7.7 dBm in the 2-14 GHz frequency band and the peak power-added efficiency(PAE)is 10.6%.The measurement results validate the proposed method as a robust DA design procedure for improving circuit performance and design efficiency.
文摘基于IBM SOI 0.18μm CMOS工艺,设计了一种高功率附加效率(PAE)的E类功率放大器,由驱动级和输出级两级构成。驱动级采用E类结构,使输出级能更好地实现开与关。输出级采用电感谐振寄生电容,提高了效率。输出级的共栅管采用自偏置的方式,防止晶体管被击穿。两级之间使用了改善输出级电压和电流交叠的网络。仿真结果表明,在2.8 V电源电压下,工作频率为2.4 GHz时,功率放大器的输出功率为23.17 d Bm,PAE为57.7%。
文摘This paper presents a new topology to implement Class F power amplifier for eliminating the on-resistance (R_(ON))effect.The time-domain and frequency-domain voltage and current waveforms for Class F amplifier are ana- lyzed using Fourier series analysis method.Considering the on-resistance effect,the formulas of the efficiency,output power,dc power dissipation,and fundamental load impedance are given from ideal current and voltage waveforms.For experimental verification,we designed and implemented a Class F power amplifier,which operates at 850 MHz using MGaAs/GaAs Heterostructure FET(HFET)device,and analyzed the measurement results.Test results show that the maximum PAE of 67% can be achieved at 28 dBm output power level.
基金Supported by the National Natural Science Foundation of China (61822407,62074161,62004213)the National Key Research and Development Program of China under (2018YFE0125700)。
