摘要
基于IBM SOI 0.18μm CMOS工艺,设计了一种高功率附加效率(PAE)的E类功率放大器,由驱动级和输出级两级构成。驱动级采用E类结构,使输出级能更好地实现开与关。输出级采用电感谐振寄生电容,提高了效率。输出级的共栅管采用自偏置的方式,防止晶体管被击穿。两级之间使用了改善输出级电压和电流交叠的网络。仿真结果表明,在2.8 V电源电压下,工作频率为2.4 GHz时,功率放大器的输出功率为23.17 d Bm,PAE为57.7%。
Based on IBM SOI 0. 18 μm CMOS process,a high PAE Class-E power amplifier was proposed. This power amplifier was composed of a driving stage and an output stage. The driving stage consisted of Class-E structure,which could turn the transistor of output stage on and off more efficiently. An inductor was used at the output stage in order to resonate the parasitic capacitance and improve the efficiency. The self-biased technique was adopted in the common-gate transistor of output stage to prevent the transistor from breakdown. An interstage network was used between the two stages to improve the overlap of current and voltage of output stage. Simuation results showed that the power amplifier could deliver an output power of 23. 17 d Bm with a PAE of 57. 7% at 2. 4 GHz operating frequency and 2. 8 V supply.
出处
《微电子学》
CSCD
北大核心
2017年第4期473-477,共5页
Microelectronics
基金
国家自然科学基金资助项目(61404166)
中国科学院国际合作局对外合作重点项目(172511KYSB20130108)
关键词
功率附加效率
E类功率放大器
输出级
驱动级
Power added efficiency（PAE）
Class-E power amplifier
Output stage
Driving stage
