A new Chien search method for shortened Reed-Solomon （RS） code is proposed, based on this, a versatile RS decoder for correcting both errors and erasures is designed. Compared with the traditional RS decoder, the we...A new Chien search method for shortened Reed-Solomon （RS） code is proposed, based on this, a versatile RS decoder for correcting both errors and erasures is designed. Compared with the traditional RS decoder, the weighted coefficient of the Chien search method is calculated sequentially through the three pipelined stages of the decoder. And therefore, the computation of the errata locator polynomial and errata evaluator polynomial needs to be modified. The versatile RS decoder with minimum distance 21 has been synthesized in the Xilinx Virtex-Ⅱ series field programmable gate array （FPGA） xe2v1000-5 and is used by coneatenated coding system for satellite communication. Results show that the maximum data processing rate can be up to 1.3 Gbit/s.展开更多
针对数字图像无线通信系统中低信噪比下图像质量的"门限效应",提出了一种基于tent map混沌系统的高阶量纠错编码方法。仿真实验中与LDPC(low-density parity-check)码、镜像Baker码对比发现,压缩图像经LDPC码处理后出现"...针对数字图像无线通信系统中低信噪比下图像质量的"门限效应",提出了一种基于tent map混沌系统的高阶量纠错编码方法。仿真实验中与LDPC(low-density parity-check)码、镜像Baker码对比发现,压缩图像经LDPC码处理后出现"门限效应",且信噪比低于2.2dB时,图像的峰值信噪比(peak signal to noise ratio,PSNR)急剧下降,而高阶量纠错码图像的PSNR随信噪比(signal to noise ratio,SNR)呈线性变化;与镜像Baker码相比,高阶量纠错码图像的PSNR有5dB的增益,并提高了编译码效率和带宽利用率,具有较强的纠错能力和较低的编译码复杂度。展开更多
With continuous technology scaling, on-chip structures are becoming more and more susceptible to soft errors. Architectural vulnerability factor （AVF） has been introduced to quantify the architectural vulnerability ...With continuous technology scaling, on-chip structures are becoming more and more susceptible to soft errors. Architectural vulnerability factor （AVF） has been introduced to quantify the architectural vulnerability of on-chip structures to soft errors. Recent studies have found that designing soft error protection techniques with the awareness of AVF is greatly helpful to achieve a tradeoff between performance and reliability for several structures （i.e., issue queue, reorder buffer）. Cache is one of the most susceptible components to soft errors and is commonly protected with error correcting codes （ECC）. However, protecting caches closer to the processor （i.e., L1 data cache （LID）） using ECC could result in high overhead. Protecting caches without accurate knowledge of the vulnerability characteristics may lead to over-protection. Therefore, designing AVF-aware ECC is attractive for designers to balance among performance, power and reliability for cache, especially at early design stage. In this paper, we improve the methodology of cache AVF computation and develop a new AVF estimation framework, soft error reliability analysis based on SimpleScalar. Then we characterize dynamic vulnerability behavior of LID and detect the correlations between L1D AVF and various performance metrics. We propose to employ Bayesian additive regression trees to accurately model the variation of L1D AVF and to quantitatively explain the important effects of several key performance metrics on L1D AVF. Then, we employ bump hunting technique to reduce the complexity of L1D AVF prediction and extract some simple selecting rules based on several key performance metrics, thus enabling a simplified and fast estimation of L1D AVF. Based on the simplified and fast estimation of L1D AVF, intervals of high L1D AVF can be identified online, enabling us to develop the AVF-aware ECC technique to reduce the overhead of ECC. Experimental results show that compared with traditional ECC technique which provides complete ECC prote展开更多
基金Sponsored by the Ministerial Level Advanced Research Foundation (20304)
文摘A new Chien search method for shortened Reed-Solomon （RS） code is proposed, based on this, a versatile RS decoder for correcting both errors and erasures is designed. Compared with the traditional RS decoder, the weighted coefficient of the Chien search method is calculated sequentially through the three pipelined stages of the decoder. And therefore, the computation of the errata locator polynomial and errata evaluator polynomial needs to be modified. The versatile RS decoder with minimum distance 21 has been synthesized in the Xilinx Virtex-Ⅱ series field programmable gate array （FPGA） xe2v1000-5 and is used by coneatenated coding system for satellite communication. Results show that the maximum data processing rate can be up to 1.3 Gbit/s.
文摘针对数字图像无线通信系统中低信噪比下图像质量的"门限效应",提出了一种基于tent map混沌系统的高阶量纠错编码方法。仿真实验中与LDPC(low-density parity-check)码、镜像Baker码对比发现,压缩图像经LDPC码处理后出现"门限效应",且信噪比低于2.2dB时,图像的峰值信噪比(peak signal to noise ratio,PSNR)急剧下降,而高阶量纠错码图像的PSNR随信噪比(signal to noise ratio,SNR)呈线性变化;与镜像Baker码相比,高阶量纠错码图像的PSNR有5dB的增益,并提高了编译码效率和带宽利用率,具有较强的纠错能力和较低的编译码复杂度。
基金Supported by the National Natural Science Foundation of China under Grant Nos. 60970036 and 60873016the National High Technology Development 863 Program of China under Grant Nos. 2009AA01Z102 and 2009AA01Z124
文摘With continuous technology scaling, on-chip structures are becoming more and more susceptible to soft errors. Architectural vulnerability factor （AVF） has been introduced to quantify the architectural vulnerability of on-chip structures to soft errors. Recent studies have found that designing soft error protection techniques with the awareness of AVF is greatly helpful to achieve a tradeoff between performance and reliability for several structures （i.e., issue queue, reorder buffer）. Cache is one of the most susceptible components to soft errors and is commonly protected with error correcting codes （ECC）. However, protecting caches closer to the processor （i.e., L1 data cache （LID）） using ECC could result in high overhead. Protecting caches without accurate knowledge of the vulnerability characteristics may lead to over-protection. Therefore, designing AVF-aware ECC is attractive for designers to balance among performance, power and reliability for cache, especially at early design stage. In this paper, we improve the methodology of cache AVF computation and develop a new AVF estimation framework, soft error reliability analysis based on SimpleScalar. Then we characterize dynamic vulnerability behavior of LID and detect the correlations between L1D AVF and various performance metrics. We propose to employ Bayesian additive regression trees to accurately model the variation of L1D AVF and to quantitatively explain the important effects of several key performance metrics on L1D AVF. Then, we employ bump hunting technique to reduce the complexity of L1D AVF prediction and extract some simple selecting rules based on several key performance metrics, thus enabling a simplified and fast estimation of L1D AVF. Based on the simplified and fast estimation of L1D AVF, intervals of high L1D AVF can be identified online, enabling us to develop the AVF-aware ECC technique to reduce the overhead of ECC. Experimental results show that compared with traditional ECC technique which provides complete ECC prote
