Degradation behaviors of 20 V NLDMOS operated under off-state avalanche breakdown conditions are presented.A constant current pulse stressing test is applied to the device.Two different degradation mechanisms are iden...Degradation behaviors of 20 V NLDMOS operated under off-state avalanche breakdown conditions are presented.A constant current pulse stressing test is applied to the device.Two different degradation mechanisms are identified by analysis of electrical data,technology computer-aided design（TCAD） simulations and charge pumping measurements.The first mechanism is attributed to positive oxide-trapped charges in the N-type drift region,and the second one is due to decreased electron mobility upon interface state formation in the drift region.Both of the mechanisms are enhanced with increasing avalanche breakdown current.展开更多
A high-side thin-layer silicon-on-insulator （SOI） pLDMOS is proposed, adopting field implant （FI） and multiple field plate （MFP） technologies. The breakdown mechanisms of back gate （BG） turn-on, surface channe...A high-side thin-layer silicon-on-insulator （SOI） pLDMOS is proposed, adopting field implant （FI） and multiple field plate （MFP） technologies. The breakdown mechanisms of back gate （BG） turn-on, surface channel punch-through, and vertical and lateral avalanche breakdown are investigated by setting up analytical models, simulating related parameters and verifying experimentally. The device structure is optimized based on the above research. The shallow junction achieved through FI technology attenuates the BG effect, the optimized channel length eliminates the surface channel punch-through, the advised thickness of the buried oxide dispels the vertical avalanche breakdown, and the MFP technology avoids premature lateral avalanche breakdown by modulating the electric field distribution. Finally, for the first time, a 300 V high-side pLDMOS is experimentally realized on a 1.5 μm thick thin-layer SOI.展开更多
This paper investigates the effect of a non-uniform gate-finger spacing layout structure on the avalanche breakdown performance of RF CMOS technology. Compared with a standard multi-finger device with uniform gate-fin...This paper investigates the effect of a non-uniform gate-finger spacing layout structure on the avalanche breakdown performance of RF CMOS technology. Compared with a standard multi-finger device with uniform gate-finger spacing, a device with non-uniform gate-finger spacing represents an improvement of 8.5% for the drain-source breakdown voltage （BVds） and of 20% for the thermally-related drain conductance. A novel compact model is proposed to accurately predict the variation of BVds with the total area of devices, which is dependent on the different finger spacing sizes. The model is verified and validated by the excellent match between the measured and simulated avalanche breakdown characteristics for a set of uniform and non-uniform gate-finger spacing arranged nMOSFETs.展开更多
An impact ionization MOSFET （IMOS） is evolved for overcoming the constraint of less than 60 mV/decade sub-threshold slope （SS） of conventional MOSFET at room temperature. In this work, first, the device performanc...An impact ionization MOSFET （IMOS） is evolved for overcoming the constraint of less than 60 mV/decade sub-threshold slope （SS） of conventional MOSFET at room temperature. In this work, first, the device performance of the p-type double gate impact ionization MOSFET （DG-IMOS） is optimized by adjusting the device design parameters. The adjusted parameters are ratio of gate and intrinsic length, gate dielectric thickness and gate work function. Secondly, the DMG （dual material gate） DG-IMOS is proposed and investigated. This DMG DG-IMOS is further optimized to obtain the best possible performance parameters. Simulation results reveal that DMG DG-IMOS when compared to DG-IMOS, shows better IoN, ION/IoFF ratio, and RF parameters. Results show that by properly tuning the lengths of two materials at a ratio of 1.5 in DMG DG-IMOS, optimized perform- ance is achieved including ION/IoFF ratio of 2.87 × 10^9 A/μm with/ON as 11.87 × 10^-4 A/μm and transconductance of 1.06× 10^-3 S/μm. It is analyzed that length of drain side material should be greater than the length of source side material to attain the higher transconductance in DMG DG-IMOS.展开更多
The static avalanche breakdown behavior of 4.5 kV high-voltage IGBT is studied by theory analysis and experiment. The avalanche breakdown behaviors of the 4.5 kV IGBTs with different backside structures are investigat...The static avalanche breakdown behavior of 4.5 kV high-voltage IGBT is studied by theory analysis and experiment. The avalanche breakdown behaviors of the 4.5 kV IGBTs with different backside structures are investigated and compared by using the curve tracer. The results show that the snap back behavior of the breakdown waveform is related to the bipolar PNP gain, which leads to the deterioration of the breakdown voltage. There are two ways to optimize the backside structure, one is increasing the implant dose of the N^＋ buffer layer, the other is decreasing the implant dose of the P^＋ collector layer. It is found that the optimized structure is effective in suppressing the snap back behavior and improving the breakdown characteristic of high voltage IGBT.展开更多
基金supported by the National Science & Technology Major Project of China(No.2009ZX01033-001-003)
文摘Degradation behaviors of 20 V NLDMOS operated under off-state avalanche breakdown conditions are presented.A constant current pulse stressing test is applied to the device.Two different degradation mechanisms are identified by analysis of electrical data,technology computer-aided design（TCAD） simulations and charge pumping measurements.The first mechanism is attributed to positive oxide-trapped charges in the N-type drift region,and the second one is due to decreased electron mobility upon interface state formation in the drift region.Both of the mechanisms are enhanced with increasing avalanche breakdown current.
基金Project supported by National Natural Science Foundation of China(Grant No.60906038)
文摘A high-side thin-layer silicon-on-insulator （SOI） pLDMOS is proposed, adopting field implant （FI） and multiple field plate （MFP） technologies. The breakdown mechanisms of back gate （BG） turn-on, surface channel punch-through, and vertical and lateral avalanche breakdown are investigated by setting up analytical models, simulating related parameters and verifying experimentally. The device structure is optimized based on the above research. The shallow junction achieved through FI technology attenuates the BG effect, the optimized channel length eliminates the surface channel punch-through, the advised thickness of the buried oxide dispels the vertical avalanche breakdown, and the MFP technology avoids premature lateral avalanche breakdown by modulating the electric field distribution. Finally, for the first time, a 300 V high-side pLDMOS is experimentally realized on a 1.5 μm thick thin-layer SOI.
基金Project supported by the State Key Development Program for Basic Research of China(No.2010CB327403)
文摘This paper investigates the effect of a non-uniform gate-finger spacing layout structure on the avalanche breakdown performance of RF CMOS technology. Compared with a standard multi-finger device with uniform gate-finger spacing, a device with non-uniform gate-finger spacing represents an improvement of 8.5% for the drain-source breakdown voltage （BVds） and of 20% for the thermally-related drain conductance. A novel compact model is proposed to accurately predict the variation of BVds with the total area of devices, which is dependent on the different finger spacing sizes. The model is verified and validated by the excellent match between the measured and simulated avalanche breakdown characteristics for a set of uniform and non-uniform gate-finger spacing arranged nMOSFETs.
文摘An impact ionization MOSFET （IMOS） is evolved for overcoming the constraint of less than 60 mV/decade sub-threshold slope （SS） of conventional MOSFET at room temperature. In this work, first, the device performance of the p-type double gate impact ionization MOSFET （DG-IMOS） is optimized by adjusting the device design parameters. The adjusted parameters are ratio of gate and intrinsic length, gate dielectric thickness and gate work function. Secondly, the DMG （dual material gate） DG-IMOS is proposed and investigated. This DMG DG-IMOS is further optimized to obtain the best possible performance parameters. Simulation results reveal that DMG DG-IMOS when compared to DG-IMOS, shows better IoN, ION/IoFF ratio, and RF parameters. Results show that by properly tuning the lengths of two materials at a ratio of 1.5 in DMG DG-IMOS, optimized perform- ance is achieved including ION/IoFF ratio of 2.87 × 10^9 A/μm with/ON as 11.87 × 10^-4 A/μm and transconductance of 1.06× 10^-3 S/μm. It is analyzed that length of drain side material should be greater than the length of source side material to attain the higher transconductance in DMG DG-IMOS.
基金Project supported by the National Major Science and Technology Special Project of China(No.2011ZX02503-003)
文摘The static avalanche breakdown behavior of 4.5 kV high-voltage IGBT is studied by theory analysis and experiment. The avalanche breakdown behaviors of the 4.5 kV IGBTs with different backside structures are investigated and compared by using the curve tracer. The results show that the snap back behavior of the breakdown waveform is related to the bipolar PNP gain, which leads to the deterioration of the breakdown voltage. There are two ways to optimize the backside structure, one is increasing the implant dose of the N^＋ buffer layer, the other is decreasing the implant dose of the P^＋ collector layer. It is found that the optimized structure is effective in suppressing the snap back behavior and improving the breakdown characteristic of high voltage IGBT.
