s:A divide- by- 12 8/ 12 9or6 4/ 6 5 dual- modulus prescaler based on new optimized structure and dynam ic circuit technique im plem ented in 0 .2 5 μm CMOS digital technology is described.New optimized structure re...s:A divide- by- 12 8/ 12 9or6 4/ 6 5 dual- modulus prescaler based on new optimized structure and dynam ic circuit technique im plem ented in 0 .2 5 μm CMOS digital technology is described.New optimized structure reduces the propagation delay and has higher operating speed.Based on this structure,an im proved D- flip- flop(DFF) using dynam ic circuit technique is proposed.A prototype is fabricated and the measured results show that this prescaler works well in gigahertz frequency range and consumes only35 m W(including three power- hungry output buffers) when the input frequency is2 .5 GHz and the power supply voltage is2 .5 V.Due to its excellent perform ance,the prescaler could be applied to many RF system s.展开更多
A low-power frequency synthesizer for GPS/Galileo L1/E1 band receivers implemented in a 0.18μm CMOS process is introduced.By adding clock-controlled transistors at latch outputs to reduce the time constant at sensing...A low-power frequency synthesizer for GPS/Galileo L1/E1 band receivers implemented in a 0.18μm CMOS process is introduced.By adding clock-controlled transistors at latch outputs to reduce the time constant at sensing time,the working frequency of the high-speed source-coupled logic prescaler supplying quadrature local oscillator signals has been increased,compared with traditional prescalers.Measurement results show that this synthesizer achieves an in-band phase noise of-87 dBc/Hz at 15 kHz offset,with spurs less than-65 dBc.The whole synthesizer consumes 6 mA in the case of a 1.8 V supply,and its core area is 0.6 mm;.展开更多
This paper describes a novel divide-by-32/33 dual-modulus prescaler （DMP）. Here, a new combination of DFF has been introduced in the DMP. By means of the cooperation and coordination among three types, DFF, SCL, TPS...This paper describes a novel divide-by-32/33 dual-modulus prescaler （DMP）. Here, a new combination of DFF has been introduced in the DMP. By means of the cooperation and coordination among three types, DFF, SCL, TPSC, and CMOS static flip-flop, the DMP demonstrates high speed, wideband, and low power consumption with low phase noise. The chip has been fabricated in a 0.18μm CMOS process of SMIC. The measured results show that the DMP＇s operating frequency is from 0.9 to 3.4 GHz with a maximum power consumption of 2.51 mW under a 1.8 V power supply and the phase noise is -134.78 dBc/Hz at 1 MHz offset from the 3.4 GHz carrier. The core area of the die without PAD is 57 x 30 #m2. Due to its excellent performance, the DMP could be applied to a PLL-based frequency synthesizer for many RF systems, especially for multi-standard radio applications.展开更多
A phase-locked loop（PLL） frequency synthesizer with a novel phase-switching prescaler and a high-Q LC voltage controlled oscillator（VCO） is presented.The phase-switching prescaler with a novel modulus control mech...A phase-locked loop（PLL） frequency synthesizer with a novel phase-switching prescaler and a high-Q LC voltage controlled oscillator（VCO） is presented.The phase-switching prescaler with a novel modulus control mechanism is much more robust on process variations.The Q factor of the inductor,I-MOS capacitors and varactors in the VCO are optimized.The proposed frequency synthesizer was fabricated by SMIC 0.13μm 1P8M MMRF CMOS technology with a chip area of 1150×2500μm^2.When locking at 5 GHz,the current consumption is 15 mA from a supply voltage of 1.2 V and the measured phase noise at a 1 MHz offset is -122.45 dBc/Hz.展开更多
A high-speed dual-modulus divide-by-32/33 prescaler has been developed using 0.25 μm CMOS technology. The source-coupled logic (SCL) structure is used to reduce the switching noise and to ameliorate the power-speed t...A high-speed dual-modulus divide-by-32/33 prescaler has been developed using 0.25 μm CMOS technology. The source-coupled logic (SCL) structure is used to reduce the switching noise and to ameliorate the power-speed tradeoff. The proposed prescaler can operate at high frequency with a low-power consumption. Based on the 2.5 V, 0.25 μm CMOS model, simulation results indicate that the maximum input frequency of the prescaler is up to 3.2 GHz. Running at 2.5 V, the circuit consumes only 4.6 mA at an input frequency 2.5 GHz.展开更多
A pulse swallowing frequency divider with low power and compact structure is presented.One of the DFFs in the divided by 2/3 prescaier is controlled by the modulus control signal,and automatically powered off when it ...A pulse swallowing frequency divider with low power and compact structure is presented.One of the DFFs in the divided by 2/3 prescaier is controlled by the modulus control signal,and automatically powered off when it has no contribution to the operation of the prescaier.The DFFs in the program counter and the swallow counter are shared to compose a compact structure,which reduces the power consumption further.The proposed multi-modulus frequency divider was implemented in a standard 65 nm CMOS process with an area of 28×22μm;.The power consumption of the divider is 0.6 mW under 1.2 V supply voltage when operating at 988 MHz.展开更多
This paper describes a 4 GHz fractional-N frequency synthesizer for a 3.1 to 5 GHz IR-UWB transceiver. Designed in a 0.18μm mixed-signal ＆ RF 1P6M CMOS process, the operating range of the synthesizer is 3.74 to 4.44...This paper describes a 4 GHz fractional-N frequency synthesizer for a 3.1 to 5 GHz IR-UWB transceiver. Designed in a 0.18μm mixed-signal ＆ RF 1P6M CMOS process, the operating range of the synthesizer is 3.74 to 4.44 GHz. By using an 18-bit third-order ∑-△ modulator, the synthesizer achieves a frequency resolution of 15 Hz when the reference frequency is 20 MHz. The measured amplitude mismatch and phase error between I and Q signals are less than 0.1 dB and 0.8° respectively. The measured phase noise is -116 dBc/Hz at 3 MHz offset for a 4 GHz output. Measured spurious tones are lower than -60 dBc. The settling time is within 80°s. The core circuit conupSigmaes only 38.2 mW from a 1.8 V power supply.展开更多
A 5-GHz CMOS programmable frequency divider whose modulus can be varied from 2403 to 2480 for 2.4-GHz ZigBee applications is presented.The divider based on a dual-modulus prescaler（DMP） and pulse-swallow counter is ...A 5-GHz CMOS programmable frequency divider whose modulus can be varied from 2403 to 2480 for 2.4-GHz ZigBee applications is presented.The divider based on a dual-modulus prescaler（DMP） and pulse-swallow counter is designed to reduce power consumption and chip area.Implemented in the 0.18-μm mixed-signal CMOS process,the divider operates over a wide range of 1-7.4 GHz with an input signal of 7.5 dBm;the programmable divider output phase noise is -125.3 dBc/Hz at an offset of 100 kHz.The core circuit without test buffer consumes 4.3 mA current from a 1.8 V power supply and occupies a chip area of approximately 0.015 mm^2.The experimental results indicate that the programmable divider works well for its application in frequency synthesizers.展开更多
This paper presents a low phase-noise fractional-N frequency synthesizer which provides an inphase/quadrature-phase（I/Q） signal over a frequency range of 220–1100 MHz for wireless networks of industrial automation...This paper presents a low phase-noise fractional-N frequency synthesizer which provides an inphase/quadrature-phase（I/Q） signal over a frequency range of 220–1100 MHz for wireless networks of industrial automation（WIA） applications. Two techniques are proposed to achieve the wide range. First, a 1.4–2.2 GHz ultralow gain voltage-controlled oscillator（VCO） is adopted by using 128 tuning curves. Second, a selectable I/Q divider is employed to divide the VCO frequency by 2 or 3 or 4 or 6. Besides, a phase-switching prescaler is proposed to lower PLL phase noise, a self-calibrated charge pump is used to suppress spur, and a detect-boosting phase frequency detector is adopted to shorten settling time. With a 200 k Hz loop bandwidth, lowest measured phase noise is 106 dBc/Hz at a 10 k Hz offset and 131 dBc/Hz at a 1 MHz offset. Fabricated in the TSMC 0.18 μm CMOS process, the synthesizer occupies a chip area of 1.2 mm^2, consumes only 15 m W from the 1.8 V power supply,and settles within 13.2 s. The synthesizer is optimized for the WIA applications, but can also be used for other short-range wireless communications, such as 433, 868, 916 MHz ISM band applications.展开更多
A 900 MHz fractional-N synthesizer is designed for the UHF transceiver. The VCO with a 4 bits capacitor bank covers 823–1061 MHz that implements 16（2^4）sub-bands. A 7/8 dual-modulus prescaler is implemented with a ...A 900 MHz fractional-N synthesizer is designed for the UHF transceiver. The VCO with a 4 bits capacitor bank covers 823–1061 MHz that implements 16（2^4）sub-bands. A 7/8 dual-modulus prescaler is implemented with a phase-switching circuit and high-speed flip–flops, which are composed of source coupled logic. The proposed synthesizer phase-locked loop is demonstrated with a 50 k Hz band width by a low 12.95 MHz reference clock, and offers a better phase noise and band width tradeoff. To reduce the out-band phase noise, a 4-levels 3-order single-loop sigma–delta modulator is applied. When its relative frequency resolution is settled to 10^-6, the testing results show that the phase noises are –120.6 dBc/Hz at 1 MHz and –95.0 dBc/Hz at 100 k Hz. The chip is2.1 mm^2 in UMC 0.18μm CMOS. The power is 36 m W at a 1.8 V supply.展开更多
文摘s:A divide- by- 12 8/ 12 9or6 4/ 6 5 dual- modulus prescaler based on new optimized structure and dynam ic circuit technique im plem ented in 0 .2 5 μm CMOS digital technology is described.New optimized structure reduces the propagation delay and has higher operating speed.Based on this structure,an im proved D- flip- flop(DFF) using dynam ic circuit technique is proposed.A prototype is fabricated and the measured results show that this prescaler works well in gigahertz frequency range and consumes only35 m W(including three power- hungry output buffers) when the input frequency is2 .5 GHz and the power supply voltage is2 .5 V.Due to its excellent perform ance,the prescaler could be applied to many RF system s.
基金Project supported by the National Municipal Sci-Tech Project of China(No.2009ZX01031-002-008)the National High Technology Research and Development Program of China(No.2007AA12Z344).
文摘A low-power frequency synthesizer for GPS/Galileo L1/E1 band receivers implemented in a 0.18μm CMOS process is introduced.By adding clock-controlled transistors at latch outputs to reduce the time constant at sensing time,the working frequency of the high-speed source-coupled logic prescaler supplying quadrature local oscillator signals has been increased,compared with traditional prescalers.Measurement results show that this synthesizer achieves an in-band phase noise of-87 dBc/Hz at 15 kHz offset,with spurs less than-65 dBc.The whole synthesizer consumes 6 mA in the case of a 1.8 V supply,and its core area is 0.6 mm;.
文摘This paper describes a novel divide-by-32/33 dual-modulus prescaler （DMP）. Here, a new combination of DFF has been introduced in the DMP. By means of the cooperation and coordination among three types, DFF, SCL, TPSC, and CMOS static flip-flop, the DMP demonstrates high speed, wideband, and low power consumption with low phase noise. The chip has been fabricated in a 0.18μm CMOS process of SMIC. The measured results show that the DMP＇s operating frequency is from 0.9 to 3.4 GHz with a maximum power consumption of 2.51 mW under a 1.8 V power supply and the phase noise is -134.78 dBc/Hz at 1 MHz offset from the 3.4 GHz carrier. The core area of the die without PAD is 57 x 30 #m2. Due to its excellent performance, the DMP could be applied to a PLL-based frequency synthesizer for many RF systems, especially for multi-standard radio applications.
基金Project supported by the Important National Science & Technology Specific Projects of China(Nos.2009ZX01031-003-002, 2010ZX03001-004)the National High Technology Research & Development Program of China(No.2009AA011605)
文摘A phase-locked loop（PLL） frequency synthesizer with a novel phase-switching prescaler and a high-Q LC voltage controlled oscillator（VCO） is presented.The phase-switching prescaler with a novel modulus control mechanism is much more robust on process variations.The Q factor of the inductor,I-MOS capacitors and varactors in the VCO are optimized.The proposed frequency synthesizer was fabricated by SMIC 0.13μm 1P8M MMRF CMOS technology with a chip area of 1150×2500μm^2.When locking at 5 GHz,the current consumption is 15 mA from a supply voltage of 1.2 V and the measured phase noise at a 1 MHz offset is -122.45 dBc/Hz.
文摘A high-speed dual-modulus divide-by-32/33 prescaler has been developed using 0.25 μm CMOS technology. The source-coupled logic (SCL) structure is used to reduce the switching noise and to ameliorate the power-speed tradeoff. The proposed prescaler can operate at high frequency with a low-power consumption. Based on the 2.5 V, 0.25 μm CMOS model, simulation results indicate that the maximum input frequency of the prescaler is up to 3.2 GHz. Running at 2.5 V, the circuit consumes only 4.6 mA at an input frequency 2.5 GHz.
基金supported by the Major State Basic Research Development Program of China(No.2010CB327403)the National Natural Science Foundation of China(No.61001066)
文摘A pulse swallowing frequency divider with low power and compact structure is presented.One of the DFFs in the divided by 2/3 prescaier is controlled by the modulus control signal,and automatically powered off when it has no contribution to the operation of the prescaier.The DFFs in the program counter and the swallow counter are shared to compose a compact structure,which reduces the power consumption further.The proposed multi-modulus frequency divider was implemented in a standard 65 nm CMOS process with an area of 28×22μm;.The power consumption of the divider is 0.6 mW under 1.2 V supply voltage when operating at 988 MHz.
基金supported by the National High Technology Research and Development Program of China(No.2007AA01Z2b2).
文摘This paper describes a 4 GHz fractional-N frequency synthesizer for a 3.1 to 5 GHz IR-UWB transceiver. Designed in a 0.18μm mixed-signal ＆ RF 1P6M CMOS process, the operating range of the synthesizer is 3.74 to 4.44 GHz. By using an 18-bit third-order ∑-△ modulator, the synthesizer achieves a frequency resolution of 15 Hz when the reference frequency is 20 MHz. The measured amplitude mismatch and phase error between I and Q signals are less than 0.1 dB and 0.8° respectively. The measured phase noise is -116 dBc/Hz at 3 MHz offset for a 4 GHz output. Measured spurious tones are lower than -60 dBc. The settling time is within 80°s. The core circuit conupSigmaes only 38.2 mW from a 1.8 V power supply.
基金supported by the National High Technology Research and Development Program of China(No.2007AA01Z2A7)the Science and Technology Program of Zhejiang Province,China(No.2008C16017).
文摘A 5-GHz CMOS programmable frequency divider whose modulus can be varied from 2403 to 2480 for 2.4-GHz ZigBee applications is presented.The divider based on a dual-modulus prescaler（DMP） and pulse-swallow counter is designed to reduce power consumption and chip area.Implemented in the 0.18-μm mixed-signal CMOS process,the divider operates over a wide range of 1-7.4 GHz with an input signal of 7.5 dBm;the programmable divider output phase noise is -125.3 dBc/Hz at an offset of 100 kHz.The core circuit without test buffer consumes 4.3 mA current from a 1.8 V power supply and occupies a chip area of approximately 0.015 mm^2.The experimental results indicate that the programmable divider works well for its application in frequency synthesizers.
基金supported by the National High Technology Research and Development Program of China(No.2011AA040102)
文摘This paper presents a low phase-noise fractional-N frequency synthesizer which provides an inphase/quadrature-phase（I/Q） signal over a frequency range of 220–1100 MHz for wireless networks of industrial automation（WIA） applications. Two techniques are proposed to achieve the wide range. First, a 1.4–2.2 GHz ultralow gain voltage-controlled oscillator（VCO） is adopted by using 128 tuning curves. Second, a selectable I/Q divider is employed to divide the VCO frequency by 2 or 3 or 4 or 6. Besides, a phase-switching prescaler is proposed to lower PLL phase noise, a self-calibrated charge pump is used to suppress spur, and a detect-boosting phase frequency detector is adopted to shorten settling time. With a 200 k Hz loop bandwidth, lowest measured phase noise is 106 dBc/Hz at a 10 k Hz offset and 131 dBc/Hz at a 1 MHz offset. Fabricated in the TSMC 0.18 μm CMOS process, the synthesizer occupies a chip area of 1.2 mm^2, consumes only 15 m W from the 1.8 V power supply,and settles within 13.2 s. The synthesizer is optimized for the WIA applications, but can also be used for other short-range wireless communications, such as 433, 868, 916 MHz ISM band applications.
文摘A 900 MHz fractional-N synthesizer is designed for the UHF transceiver. The VCO with a 4 bits capacitor bank covers 823–1061 MHz that implements 16（2^4）sub-bands. A 7/8 dual-modulus prescaler is implemented with a phase-switching circuit and high-speed flip–flops, which are composed of source coupled logic. The proposed synthesizer phase-locked loop is demonstrated with a 50 k Hz band width by a low 12.95 MHz reference clock, and offers a better phase noise and band width tradeoff. To reduce the out-band phase noise, a 4-levels 3-order single-loop sigma–delta modulator is applied. When its relative frequency resolution is settled to 10^-6, the testing results show that the phase noises are –120.6 dBc/Hz at 1 MHz and –95.0 dBc/Hz at 100 k Hz. The chip is2.1 mm^2 in UMC 0.18μm CMOS. The power is 36 m W at a 1.8 V supply.
